Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-138 Freescale Semiconductoris not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD or a setuparriving during the prime operation. If a new setup packet is indicated after the ENDPTPRIME bit iscleared, then the transfer descriptor can be freed and the DCD must reinterpret the setup packet.Should a setup arrive after the data stage is primed, the device controller will automatically clear the primestatus (ENDPTSTATUS) to enforce data coherency with the setup packet.NOTEThe MULT field in the dQH must be set to ‘00’ for bulk, interrupt, andcontrol endpoints.NOTEError handling of data phase packets is the same as bulk packets describedpreviously.24.11.3.5.3 Status PhaseSimilar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and primethe endpoint for the status phase. The DCD must also perform the same checks of the ENDPTSETUPSTATas described above in the data phase.NOTEThe MULT field in the dQH must be set to ‘00’ for bulk, interrupt, andcontrol endpoints.NOTEError handling of data phase packets is the same as bulk packets describedpreviously.24.11.3.5.4 Control Endpoint Bus Response MatrixTable 24-86 shows the device controller response to packets on a control endpoint according to the devicecontroller state.Table 24-86. Control Endpoint Bus Response MatrixTokenTypeEndpoint State SetupLockoutStall Not Primed Primed Underflow OverflowSetup ACK ACK ACK N/A SYSERR11 SYSERR—System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive.In STALL NAK Transmit BS Error 22 Force Bit Stuff Error.N/A N/AOut STALL NAK Receive + NYET/ACK 33 NYET/ACK—NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol thenACK.N/A NAK N/APing STALL NAK ACK N/A N/A N/AInvalid Ignore Ignore Ignore Ignore Ignore Ignore
