IDE and Flash Media InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 13-11NOTEIf CS2POST is set to 2, every write cycle is lengthened with 1 clock. IfCS2POST is set to 3, every write cycle is lengthened with 2 clocks. Thismarginally reduces throughput.NOTEA 3-clock cycle hold time to any MCF5253 external access has been added.As a result, hold time address to TA and write data to TA is not an issue.13.4 Flash Media InterfaceThe MCF5253 is capable of interfacing with Sony Memory Stick and Multi-Media Card (MMC) / SecureDigital (SD) flash cards. The interface can handle one of them at any given time, but not both at the sametime.Figure 13-8. Flash Media Block DiagramIn the Flash Media interface there are four blocks:1. The clock generator generates the clock to the flash device2. The Processor interface handles interrupts and processor I/O3. Interface shift register 14. Interface shift register 2Each interface shift register is a serial interface to the Flash Media device. The two interfaces share theclock generating circuitry.The flash media interface can operate in two modes.1. MemoryStick mode. In this mode it is possible to connect two Sony Memory Stick cards. Eachinterface can handle one Memory Stick card. The two interfaces share only the clock generatinglogic, all other logic is fully independent.ClockGenerator Interface shiftregister 1Interface shiftregister 2ProcessorInterfacesclk_out_pinbs1_pinsdata3_pinsdata2_pinsdata1_pinsdata0_sdio1_pinbs2_pincmd_sdio2_pinstopclock1stopclock2SCLKOUTBS1SDATA3SDATA2SDATA1SDATA0_SDIO1BS2CMD_SDIO2
