Background Debug Mode (BDM) InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 20-2920.4.1.2 Debug Module Hardware20.4.1.2.1 Reuse of Debug Module Hardware (Rev. A)The debug module implementation provides a common hardware structure for both BDM and breakpointfunctionality. Several structures are used for both BDM and breakpoint purposes. Table 20-18 identifiesthe shared hardware structures.The shared use of these hardware structures means the loading of the register to perform any specifiedfunction is destructive to the shared function. For example, if an operand address breakpoint is loaded intothe debug module, a BDM command to access memory overwrites the breakpoint. If a data breakpoint isconfigured, a BDM write command overwrites the breakpoint contents.20.5 Debug Module Memory Map and Register DefinitionsIn addition to the existing BDM commands that provide access to the processor’s registers and the memorysubsystem, the debug module contains nine registers to support the required functionality. All of theseregisters are treated as 32-bit quantities, regardless of the actual number of bits in the implementation. Theregisters, known as the debug control registers, are accessed through the BDM port using two new BDMcommands: WDMREG and RDMREG. These commands contain a 4-bit field, DRc, which specifies theparticular register being accessed.These registers are also accessible from the processor’s supervisor programming model through theexecution of the WDEBUG instruction. Thus, the breakpoint hardware within the debug module may beaccessed by the external development system using the serial interface, or by the operating system runningon the processor core. It is the responsibility of the software to guarantee that all accesses to these resourcesare serialized and logically consistent. The hardware provides a locking mechanism in the CSR to allowthe external development system to disable any attempted writes by the processor to the breakpointregisters (setting IPW = 1). The BDM commands must not be issued if the ColdFire processor is accessingthe debug module registers using the WDEBUG instruction.Table 20-18. Shared BDM/Breakpoint HardwareRegister BDM Function Breakpoint FunctionAATR Bus Attributes for All Memory Commands Attributes for Address BreakpointABHR Address for All Memory Commands Address for Address BreakpointDBR Data for All BDM Write Commands Data for Data Breakpoint
