MCF5253 Reference Manual, Rev. 1Freescale Semiconductor 21-1Chapter 21IEEE 1149.1 Test Access Port (JTAG)This chapter discussed the JTAG signal descriptions, TAP controller, register descriptions, and how todisable the standard operation.The MCF5253 JTAG test architecture implementation currently supports circuit board test strategies thatare based on the IEEE standard. This architecture provides access to all of the data and chip control pinsfrom the board edge connector through the standard four-pin test access port (TAP) and the active-lowJTAG reset pin, TRST. The test logic uses static design and is wholly independent of the system logic,except where the JTAG is subordinate to other complimentary test modes (see Chapter 20, “BackgroundDebug Mode (BDM) Interface,” for more information). When in subordinate mode, the JTAG test logic isplaced in reset and the TAP pins can be used for other purposes in accordance with the rules andrestrictions set forth using a JTAG compliance-enable pin.21.1 FeaturesThe MCF5253 JTAG implementation can do the following:• Perform boundary-scan operations to test circuit board electrical continuity• Bypass the MCF5253 by reducing the shift register path to a single cell• Sample the MCF5253 system pins during operation and transparently shift out the result• Set the MCF5253 output drive pins to fixed logic values while reducing the shift register path to asingle cell• Protect the MCF5253 system output and input pins from backdriving and random toggling (suchas during in-circuit testing) by placing all system signal pins to high- impedance stateNOTEThe IEEE Standard 1149.1 test logic cannot be considered completelybenign to those planning not to use JTAG capability. Users must observecertain precautions to ensure that this logic does not interfere with system ordebug operation. Refer to Section 21.7, “Disabling IEEE 1149.1A StandardOperation.”21.2 Block DiagramFigure 21-1 is a block diagram of the MCF5253 implementation of the 1149.1A IEEE Standard. The testlogic includes several test data registers, an instruction register, instruction register control decode, and a16-state dedicated TAP controller.
