UART ModulesMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 15-9framing error (FE), overrun error (OE), and received break (RB) conditions (if any) set error and breakflags in the USR at the received character boundary and are valid only when the RxRDY bit in the USR isset.If a break condition is detected (RxD is low for the entire character including the stop bit), a character ofall zeros is loaded into the receiver holding register and the Receive Break (RB) and RxRDY bits in theUSR are set. The RxD signal must return to a high condition for at least one-half bit time before a searchfor the next start bit begins.The receiver will detect the beginning of a break in the middle of a character if the break persists throughthe next character time. When the break begins in the middle of a character, the receiver places thedamaged character in the receiver first-in-first-out (FIFO) stack and sets the corresponding errorconditions and RxRDY bit in the USR. The break persists until the next character time, the receiver placesan all-zero character into the receiver FIFO, and sets the corresponding RB and RxRDY bits in the USR.Interrupts can be enabled on receive break.15.3.2.3 Receiver FIFOThe FIFO is used in the UART receiver buffer logic. The FIFO consists of three receiver holding registers.The receive buffer consists of the FIFO and a receiver shift register connected to the RxD (refer toFigure 15-4). Data is assembled in the receiver shift register and loaded into the top empty receiver holdingregister position of the FIFO. Thus, data flowing from the receiver to the CPU is quadruple buffered.In addition to the data byte, three status bits, parity error (PE), framing error (FE), and received break (RB)are appended to each data character in the FIFO; overrun error (OE) is not appended. By programming theerror-mode bit (ERR) in the channel's mode register (UMR1), status can be provided in character or blockmodes.The RxRDY bit in the USR is set whenever one or more characters are available to be read by the CPU.A read of the receiver buffer produces an output of data from the top of the FIFO. After the read cycle, thedata at the top of the FIFO and its associated status bits are ‘'popped,'’ and the receiver shift register canadd new data at the bottom of the FIFO. The FIFO-full status bit (FFULL) is set if all three stack positionsare filled with data. Either the RxRDY or FFULL bit can be selected to cause an interrupt.Character and block modes are two error modes that can be selected within the UMR.In the character mode, status provided in the USR is given on a character-by-character basis and thusapplies only to the character at the top of the FIFO. In the block mode, the status provided in the USR isthe logical OR of all characters coming to the top of the FIFO since the last reset error command. Acontinuous logical OR function of the corresponding status bits is produced in the USR as each characterreaches the top of the FIFO.The block mode is useful in applications where the software overhead of checking each character's errorcannot be tolerated. In this mode, entire messages are received and only one data integrity check isperformed at the end of the message. This mode has a data-reception speed advantage; however, eachcharacter is not individually checked for error conditions by software. If an error occurs within themessage, the error is not recognized until the final check is performed, and no indication exists as to whichmessage character is at fault.
