UART ModulesMCF5253 Reference Manual, Rev. 115-24 Freescale Semiconductor15.4.8 Input Port Change Registers (UIPCRn)The UIPCR registers show the current state and the change-of-state for the CTS pin. (Note: not availableon UART2).15.4.9 Auxiliary Control Registers (UACRn)The UART auxiliary control registers control the input enable.Table 15-13. Transmitter Buffer (UTBn) Register Field DescriptionsBit Name DescriptionTB7–TB0 These bits contain the character in the transmitter buffer.Address MBAR + $1D0 (UIPCR0)MBAR + $210 (UIPCR1)MBAR2 + $C10 (UIPCR2)Access: User read only7 6 5 4 3 2 1 0R COS CTSWReset 0 0 0 0 1 1 1 1Figure 15-15. Input Port Change Register (UIPCRn)Table 15-14. Input Port Change Register (UIPCRn) Field DescriptionsField Description7–5,3–1Reserved4COSChange-of-State1 A change-of-state (high-to-low or low-to-high transition), lasting longer than 25–50 μs has occurred at the CTS input.When this bit is set, the UART Auxiliary Control Register (UACR) can be programmed to generate an interrupt tothe CPU.0 No change-of-state has occurred since the last time the CPU read the UART Input Port Change Register (UIPCR).A read of the UIPCR also clears the UART Interrupt Status Register (UISR)COS bit.0CTSCurrent StateStarting two serial clock periods after reset, the CTS bit reflects the state of the CTS pin. If the CTS pin is detected asasserted at that time, the COS bit is set, which initiates an interrupt if the Input Enable Control (IEC) bit of the UACRregister is enabled.1 The current state of the CTS input is logic one.0 The current state of the CTS input is logic zero.Note: Not available on UART2
