Bus OperationMCF5253 Reference Manual, Rev. 18-6 Freescale Semiconductorterminate in an error. If a match is found for any chip selects or DRAM, the bus cycle will be executed onthe external bus. Chip select accesses follow timing diagrams given in this section. DRAM accesses aredifferent. They are described in the section on the DRAM controller.Table 8-5 shows the type of access as a function of match in various memory space programming registers.Basic operation of the MCF5253 bus is a three-clock bus cycle. During the first clock, the address isdriven. CSx is asserted at the falling edge of the clock to indicate that address and attributes are valid andstable. Data and TA are sampled during the second clock of a bus-read cycle. TA is generated internally inthe chip select module.During a read, the external device provides data and is sampled at the rising edge at the end of the secondbus clock. This data is concurrent with TA, which is also sampled at the rising edge of the clock. Duringa write, the MCF5253 drives data from the rising clock edge at the end of the first clock to the rising clockedge at the end of the bus cycle.Users can add wait states between the first and second clocks by delaying the assertion of TA. This refersto internal transfers only and not the write cycles. This is done by programming the relevant chip selectregisters. If “0000” is programmed in the WS field of the relevant chip select register, a no wait cycleresults. If n is programmed in the WS field, n wait cycles will result. The last clock of the bus cycle useswhat would be an idle clock between cycles to provide hold time for address and write data. Figure 8-4and Figure 8-6 show the basic read and write operations.8.5.2 Read CycleThe Read cycle as shown in Figure 8-3, will occur if the wait cycle field (WS) in the Chip Select ControlRegister (CSR) is programmed to value “0000”. The CS low time is increased with n clocks if n isprogrammed into the WS field.During a read cycle, the MCF5253 receives data from memory or from a peripheral device. The read cycleflowchart is shown in Figure 8-3 while the read cycle timing diagram is shown in Figure 8-4.Table 8-5. Accesses by MatchesKRAMMatchesSBC 2MatchesSBC 1MatchesNumber ofChip SelectsRegisterMatchesNumber ofDRAMControllerRegisterMatchesType of Accessyes any any any any on-chip SRAMno yes any any any SBC 2no no yes none none SBC 1no no no single none as defined by Chip-Select control registerno no no none single as defined by DRAM control registerno no no none none UndefinedAll other combinations Undefined
