Synchronous DRAM Controller ModuleMCF5253 Reference Manual, Rev. 17-18 Freescale Semiconductor7.6.1 SDRAM Interface ConfigurationTo interface this component to the MCF5253 DRAM controller, use the connection table that correspondsto a 16-bit port size with 8 columns (Figure 7-14). Two pins select one of four banks when the part isfunctional. Table 7-13 shows the proper hardware hook-up.7.6.2 DCR InitializationAt power-up, the DCR has the following configuration if synchronous operation and SDRAM addressmultiplexing is desired.This configuration results in a value of 0x8012 for DCR, as shown in Table 7-14.Table 7-13. SDRAM Hardware ConnectionsMCF5253 Pins A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20/A24 A21 A22SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 = CMD A11 BA0 BA115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Field SO NAM COC IS RTIM RCSetting 1 – 0 0 0 0 0 0 0 0 0 1 0 0 1 0(hex) 8 0 1 2Figure 7-13. Initialization Values for DCRTable 7-14. DCR Initialization ValuesBits Setting Description15SO1 Indicating synchronous operation14 x Don’t care (reserved)13NAM0 Indicating SDRAM controller multiplexes address lines internally12COC0 BCLKE is used as clock enable instead of command bit because user is not multiplexing address linesexternally and requires external command feed.11IS0 At power-up, allowing power self-refresh state is not appropriate because registers are being set up.10–9RTIM00 Because t RC value is 70 nS, indicating a 3-clock refresh-to- ACTV timing.8–0RC0x12 Specification indicates auto-refresh period for 4096 rows to be 64 mS or refresh every 15.625 μs for each row,or 312 bus clocks at 40MHz. Because DCR[RC] is incremented by 1 and multiplied by 16, RC = (312 busclocks/16) -1 = 18.56 = 0x12
