Chip Select ModuleMCF5253 Reference Manual, Rev. 110-8 Freescale Semiconductor10.4.2.3 Chip Select Control RegisterCSCRx control the auto acknowledge, external master support, port size, burst capability, and activationof each of the chip selects.For CSCR0, bits BSTR, and BSTW are initialized to 0 by reset; bits WS[3:0] and BEM are initialized to1 by reset; while AA, PS1, and PS0 are loaded with “110”, respectively at reset. For CSCR1 to CSCR4none of the bits are initialized at reset. These are shown in Figure 10-3 and Figure 10-4.CS0 is the global (boot) chip select which allows address decoding for boot ROM before systeminitialization occurs. Its operation differs from the other external chip select outputs following a systemreset.6–1AM, C/I, SC,SD, UC, UDThese fields mask specific address spaces.If an address space mask bit were cleared, an access to a location in that address space can activate thecorresponding chip select. If an address space mask bit were set, an access to a location in that addressspace becomes a regular external bus access, and no chip select is activated.AM: Alternate master access (DMA)C/I: Interrupt cycle accessSC: Supervisor code accessSD: Supervisor data accessUC: User code accessUD: User data accessFor each address space mask bit (AM, C/I, SC, SD, UC, UD):0 Do not mask this address space for the chip select. An access using the chip select can occur for thisaddress space.1 Mask this address space from the chip select activation. If this address space is accessed, no chip selectactivation occurs on the external cycle.0VThe Valid bit indicates that the contents of its address register, mask register, and control register are valid.The programmed chip selects do not assert until the V-bit is set (except for CS0 which acts as the global(boot) chip select—see Section 10.3.3, “Global Chip-Select Operation.”)A reset clears the V-bit in each CSMR.0 Chip select invalid1 Chip select validAddress MBAR + 0x8A (CSCR0) Access: User read/write15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R WS3 WS2 WS1 WS0 AA PS1 PS0 BSTR BSTWWReset – – 1 1 1 1 – 1 1 0 – 0 0 – – 0Figure 10-3. Chip Select Control Register (CSCR0)Table 10-4. Chip Select Mask Register (CSMRx) Field Descriptions (continued)Field Description
