Phase-Locked Loop and Clock DividersMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 4-7Note: MCLK1 will output a clock signal just after reset, it can be configured as GPIO if so desired. The frequency of the clock willbe the same as CRIN prior to initialization of the PLL.Note: The AUDIO_CLOCK can also be derived from the LRCK3/AUDIOCLK/GPIO43 pin.The multiplexer that switches AUDIO_CLOCK between CRIN and CRIN/2 is glitch free. No reset isneeded after switching audio clock. For the MCLK1 and MCLK2 clocks, the divide by 2 is 50% dutycycle, divide by 3 is 33% duty cycle, and divide by 4 is 50% duty cycle.4.5 Reduced Power ModeTo save power, it is recommended that users reduce the frequency of the CPU clocks. This is done byreprogramming the PLLCONFIG register.The PLL is also configured with a power down bit. This bit, when set to 1, this sets the PLL to Sleep mode.In Sleep mode, the VCXO is turned off.NOTEThe PLL must go through the re-locking procedure when it is re-enabled.4.6 Sleep / Wake-up ModeThe device can be put in a low power Sleep mode, where all internal clocks and all on-chip functions arestopped. In Sleep mode, the only block still functional is the on-chip voltage regulator. All the other analogfeatures are put in to low-power operation and all digital functions are stopped.011 1 1 CRIN CRIN/2 CRIN100 1 1 CRIN CRIN CRIN/2101 1 1 CRIN CRIN CRIN110 1 1 CRIN CRIN/2 CRIN/2111 1 1 CRIN CRIN/2 CRIN000 1 0 CRIN/2 CRIN CRIN/2001 1 0 CRIN/2 CRIN CRIN010 1 0 CRIN/2 CRIN/2 CRIN/2011 1 0 CRIN/2 CRIN/2 CRIN100 1 0 CRIN/2 CRIN CRIN/2101 1 0 CRIN/2 CRIN CRIN110 1 0 CRIN/2 CRIN/2 CRIN/2111 1 0 CRIN/2 CRIN/2 CRINTable 4-7. PLLCR Bit Fields (continued)PLLCR[CLSEL](Bits 30–28)PllCR CRsel(Bit 23)pllCR ConfigAudiosel(Bit 22)AUDIO_CLOCK MCLK2 MCLK1
