General Purpose Timer ModulesMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 11-3When the timer reaches the reference value, the REF bit in the TER register is set and issues an interruptif the output reference interrupt (ORI) enable bit in TMR is set.11.5.3 Configuring the Timer for Output Mode (TIMER0)Timer0 can send an output signal on the timer output (TOUT0) pin when it reaches the reference value asselected by the output mode (OM) bit in the TMR. This signal can be an active-low pulse or a toggle ofthe current output under program control.11.6 General-Purpose Timer Memory Map and Register DefinitionsUsers can modify the timer registers at any time. Table 11-1 shows the timer memory map.11.6.1 Timer Mode Registers (TMR0, TMR1)The TMR is a 16-bit memory-mapped register. This register programs the various timer modes and iscleared by reset.Table 11-1. Memory Map for General-Purpose TimersTimer 0 Address Timer 1 Address Timer Module RegistersMBAR+$140 MBAR+$180 Timer Mode Register (TMRn)MBAR+$144 MBAR+$184 Timer Reference Register (TRRn)MBAR+$148 MBAR+$188 Timer Capture Register (TCRn)MBAR+$14C MBAR+$18C Timer Counter (TCNn)MBAR+$151 MBAR+$191 Reserved Timer Event Register (TERn)Address MBAR+$140MBAR+$180Access: Supervisor or User read/write15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R PRESCALER VALUE (PS7–PS0) CE1 CE0 OM ORI FRR CLK1 CLK0 RESETWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 11-2. Timer Mode Register (TMRn)Table 11-2. Timer Mode Register (TMRn) Field DescriptionsBit Name Description15–8PSThe Prescaler Value is programmed to divide the clock input by values from 1 to 256. The value 00000000 dividesthe clock by 1; the value 11111111 divides the clock by 256.Prescalar value = $[PS7 – PS0] + 17–6CEThese bits have no function and should be set to 00.
