Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-4 Freescale Semiconductor24.5.3 System ClockThe core logic of the USB controller is clocked with a gated copy of the system clock (CPU clock / 2).This clock can be disabled when the USB module is not in use or suspended. Note however that this clockmust be enabled prior to accessing any register in the USB controller. Failing to do so will result in anunterminated bus cycle which will lock the bus.The suspend/resume circuit that detects wake-up events on the bus remains active, even when the USBclock is turned off.24.6 Memory Map and Register DefinitionsThis section provides the memory map and detailed descriptions of all USB interface registers. Thememory map of the USB interface is shown in Table 24-2.Table 24-2. USB Interface Memory MapOffset Register Access Reset Section/PageMBAR2 + 0x600 ID—Identification register R 0x0040_FA05 24.6.1.1/24-5MBAR2 + 0x604 HWGENERAL—General hardware parameters R 0x000_0115 24.6.1.2/24-7MBAR2 + 0x608 HWHOST—Host hardware parameters R 0x1002_0001 24.6.1.3/24-8MBAR2 + 0x60c HWDEVICE—Device hardware parameters R 0x0000_0009 24.6.1.4/24-8MBAR2 + 0x610 HWTXBUF—TX buffer hardware parameters R 0x8004_0604 24.6.1.5/24-9MBAR2 + 0x614 HWRXBUF—RX buffer hardware parameters R 0x0000_0504 24.6.1.6/24-10MBAR2 + 0x703 CAPLENGTH—Capability Length Register R 0x40 24.6.2.1/24-11MBAR2 + 0x700 HCIVERSION—Host Interface Version Number R 0x0100 24.6.2.2/24-11MBAR2 + 0x704 HCSPARAMS—Host Control Structural parameters R 0x0001_0011 24.6.2.3/24-12MBAR2 + 0x708 HCCPARAMS—Host Control Capability parameters R 0x0000_0006 24.6.2.4/24-12MBAR2 + 0x722 DCIVERSION—Dev. Interface Version Number R 0x0001 24.6.2.5/24-14MBAR2 + 0x724 DCCPARAMS—Dev. Control Capability parameters R 0x0000_0184 24.6.2.6/24-14MBAR2 + 0x740 USBCMD—USB Command R/W 0x0008_0000 24.6.3.1/24-15MBAR2 + 0x744 USBSTS—USB Status R/W 0x0000_0080 24.6.3.2/24-18MBAR2 + 0x748 USBINTR—USB Interrupt Enable R/W 0x0000_0000 24.6.3.3/24-20MBAR2 + 0x74c FRINDEX—USB Frame Index R/W 0x0000_0000 24.6.3.4/24-21MBAR2 + 0x754 PERIODICLISTBASE—Frame List Base Address R/W 0x0000_0000 24.6.3.6/24-23MBAR2 + 0x758 ASYNCLISTADDR—Next Asynchronous List Address R/W 0x0000_0000 24.6.3.8/24-24MBAR2 + 0x75c TTCTRL—TT status and control R/W 0x0000_0000 –MBAR2 + 0x760 BURSTSIZE—Programmable DMA Burst Size R/W 0x0000_0404 24.6.3.10/24-26MBAR2 + 0x764 TXFILLTUNING—Host TT Xmit Pre-buffer Packet Tuning R/W 0x0000_0000 24.6.3.11/24-27MBAR2 + 0x780 CONFIGFLAG—Configured Flag Register R 0x0000_0001 24.6.3.12/24-29
