Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-82 Freescale Semiconductor-- software is unlinking a consecutive series of-- queue heads, QHeadNext must be set by software to-- the queue head remaining in the schedule.---- This algorithm unlinks a queue head from a circular list--pQueueHeadPrevious.HorizontalPointer = pQueueHeadToUnlink.HorizontalPointerpQueueHeadToUnlink.HorizontalPointer = pQHeadNextEnd UnlinkQueueHeadIf the software removes the queue head with the H-bit set, it must select another queue head still linkedinto the schedule and set its H-bit. This should be completed before removing the queue head. Therequirement is that the software keep one queue head in the asynchronous schedule, with its H-bit set. Atthe point the software has removed one or more queue heads from the asynchronous schedule, it isunknown whether the host controller has a cached pointer to them. Similarly, it is unknown how long thehost controller might retain the cached information, as it is implementation dependent and may be affectedby the actual dynamics of the schedule load. Therefore, once the software has removed a queue head fromthe asynchronous list, it must retain the coherency of the queue head (link pointers). It cannot disturb theremoved queue heads until it knows that the host controller does not have a local copy of a pointer to anyof the removed data structures.The method the software uses to determine when it is safe to modify a removed queue head is to handshakewith the host controller. The handshake mechanism allows the software to remove items from theasynchronous schedule, then execute a simple, lightweight handshake that is used by the software as a keythat it can free (or reuse) the memory associated the data structures it has removed from the asynchronousschedule.The handshake is implemented with three bits in the host controller. The first bit is a command bit(Interrupt on Async Advance Doorbell bit in the USBCMD register) that allows the software to inform thehost controller that something has been removed from its asynchronous schedule. The second bit is a statusbit (Interrupt on Async Advance bit in the USBSTS register) that the host controller sets after it hasreleased all on-chip state that may potentially reference one of the data structures just removed. When thehost controller sets this status bit, it also clears the command bit. The third bit is an interrupt enable(Interrupt on Async Advance bit in the USBINTR register) that is matched with the status bit. If the statusbit is set and the interrupt enable bit is set, then the host controller asserts a hardware interrupt.Figure 24-49 illustrates a general example where consecutive queue heads (B and C) are unlinked fromthe schedule using the algorithm above. Before the unlink operation, the host controller has a copy ofqueue head A.The unlink algorithm requires that as the software unlinks each queue head, the unlinked queue head isloaded with the address of a queue head that will remain in the asynchronous schedule.When the host controller observes that doorbell bit being set, it makes a note of the local reachableschedule information. In this example, the local reachable schedule information includes both queue heads(A & B). It is sufficient that the host controller can set the status bit (and clear the doorbell bit) as soon asit has traversed beyond current reachable schedule information (that is, traversed beyond queue head (B)in this example).
