Phase-Locked Loop and Clock DividersMCF5253 Reference Manual, Rev. 14-4 Freescale Semiconductor1. If this bit is 0, the PLL is by-passed, and CRIN is sent directly to the CPU and MCLKs. Always set the PLL to Bypass modebefore changing any other bit in this register. Clock frequencies described in other notes are only valid when this bit is set 1.2. PLL may require up to 10 mS to lock3. Fin is input frequency to PLL. Nominal setting for CRsel is ‘1’ for 33.8688 MHz X-tal, ‘0’ for 16.9344 MHz or 11.2896MHz X-tal.4. Faudio is clock for audio interfaces. Typically 11.2896 or 16.9344 or 22.579 or 33.8688 MHz.5. Fvcxo = Fin × (2 × VCXODIV)/ (PLLDIV)6. FVCXOOut depends on Fvcxo (note 5) and vcxoout setting as shown in Table 4-3.7. Field determines frequency output on MCLK1 and MCLK2 pinsWhen frequency is CRIN/2 or CRIN/4, duty cycle is 50%. When frequency is CRIN/3, duty cycle is 33%.8. Fcpu = FVCXOOUT / CPUDIV; Fcpu is the frequency the processor is running at.1 Reserved, should be cleared. –0PLLBYP0 Bypass PLL and dividers1 Switch to PLL after PLL is locked1, 2Table 4-3. Vcxoout SettingsVcxooutSetting FVCXOOut0 Don’t use1 Fvcxo2 Fvcxo/23 Don’t useTable 4-4. Crsel and CLsel SettingsCrsel CLsel FrequencyMCLK1FrequencyMCLK20 000 CRIN CRIN/20 001 CRIN CRIN0 010 CRIN/2 CRIN/20 011 CRIN/2 CRIN1 000 CRIN/2 CRIN/21 001 CRIN/2 CRIN/31 010 CRIN/2 CRIN/41 011 CRIN/3 CRIN/21 100 CRIN/3 CRIN/31 101 CRIN/3 CRIN/41 110 CRIN/4 CRIN/21 111 CRIN/4 CRIN/3Table 4-2. PLLCONFIG Field Descriptions (continued)Field Description Notes
