ColdFire CoreMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 3-72. The processor determines the exception vector number. For all faults except interrupts, theprocessor performs this calculation based on the exception type. For interrupts, the processorperforms an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from aperipheral device. The IACK cycle is mapped to a special acknowledge address space with theinterrupt level encoded in the address.3. The processor saves the current context by creating an exception stack frame on the system stack.The CF2 Core supports a single stack pointer in the A7 address register; therefore, there is nonotion of separate supervisor or user stack pointers. As a result, the exception stack frame is createdat a 0-modulo-4 address on the top of the current system stack. Additionally, the processor uses asimplified fixed-length stack frame for all exceptions. The exception type determines whether theprogram counter placed in the exception stack frame defines the location of the faulting instruction(fault) or the address of the next instruction to be executed (next).4. The processor calculates the address of the first instruction of the exception handler. By definition,the exception vector table is aligned on a 1-megabyte boundary. This instruction address isgenerated by fetching an exception vector from the table located at the address defined in the vectorbase register. The index into the exception table is calculated as (4 x vector number). Once theexception vector has been fetched, the contents of the vector determine the address of the firstinstruction of the desired handler. After the instruction fetch for the first opcode of the handler hasbeen initiated, exception processing terminates and normal instruction processing continues in thehandler.ColdFire 5200 processors support a 1024-byte vector table aligned on any 1-megabyte address boundary(see Table 3-5). The table contains 256 exception vectors where the first 64 are defined by Freescale andthe remaining 192 are user-defined interrupt vectors.The CF2 Core processor inhibits sampling for interrupts during the first instruction of all exceptionhandlers. This allows any handler to effectively disable interrupts, if necessary, by raising the interruptmask level contained in the status register.Table 3-5. Exception Vector AssignmentsVectorNumbers(s)VectorOffset (HEX)Stacked 1, 2ProgramCounterAssignment0 $000 – Initial stack pointer1 $004 – Initial program counter2 $008 Fault Access error3 $00C Fault Address error4 $010 Fault Illegal instruction5 $014 Fault Divide by zero6–7 $018-$01C – Reserved8 $020 Fault Privilege violation9 $024 Next Trace10 $028 Fault Unimplemented line-a opcode
