Background Debug Mode (BDM) InterfaceMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 20-37Access: User read/write31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R STATUS FOF TRG HALT BKPT HRLBKD PCD IPWWReset 0 0 0 0 0 0 0 0 – – – – – – – 015 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R MAP TRC EMU DDC UHE BTB NPL IPI SSMWReset 0 0 0 0 0 0 0 0 0 0 0 0 – – – –Note: The CSR is a write only register from the programming model. It can be read from and written to through the BDM port.Figure 20-37. Configuration/Status Register (CSR)Table 20-22. Configuration/Status Register (CSR) Field DescriptionsField Description31–28STATUSThe Breakpoint Status 4-bit field provides read-only status information concerning the hardware breakpoints.This field is defined as follows:000x No breakpoints enabled001x Waiting for level 1 breakpoint010x Level 1 breakpoint triggered101x Waiting for level 2 breakpoint110x Level 2 breakpoint triggeredThe breakpoint status is also output on the DDATA port when it is not busy displaying other processor data. Awrite to the TDR resets this field.27FOFIf the read-only Fault-on-Fault status bit is set, a catastrophic halt has occurred and forced entry into BDM.This bit is cleared on a read from the CSR.26TRGIf the read-only Hardware Breakpoint Trigger status bit is set, a hardware breakpoint has halted the processorcore and forced entry into BDM. This bit is cleared by reading CSR.25HALTIf the read-only Processor Halt status bit is set, the processor has executed the HALT instruction and forcedentry into BDM. This bit is cleared by reading the CSR.24BKPTIf the read-only Breakpoint Assert status bit is set, the BKPT signal was asserted, forcing the processor intoBDM. This bit is cleared on a read from the CSR.23–20HRLThis hardware revision level indicates the level of functionality implemented in the debug module. Thisinformation could be used by an emulator to identify the level of functionality supported. A zero value wouldindicate the initial debug functionality. For example, a value of 1 would represent Revision A while a value of0 would represent the earlier release of Revision A.18BKDThe Disable the Normal BKPT Input Signal Functionality bit is used to disable the normal BKPT input signalfunctionality, and allow the assertion of this pin to generate a debug interrupt. If set, the assertion of the BKPTpin is treated as an edge-sensitive event. Specifically, a high-to-low edge on the BKPT pin generates a signalto the processor indicating a debug interrupt. The processor makes this interrupt request pending until thenext sample point occurs. At that time, the debug interrupt exception is initiated. In the ColdFire architecture,the interrupt sample point occurs once per instruction. There is no support for any type of “nesting” of debuginterrupts.17PCDIf set, the PSTCLK Disable bit disables the generation of the PSTCLK output signal, and forces this signal toremain quiescent.
