Background Debug Mode (BDM) InterfaceMCF5253 Reference Manual, Rev. 120-38 Freescale Semiconductor16IPWIf set, the Inhibit Processor Writes to Debug Registers bit inhibits any processor-initiated writes to the debugmodule’s programming model registers. This bit can only be modified by commands from the externaldevelopment system.15MAPIf set, the Force Processor References in Emulator Mode bit forces the processor to map all references whilein emulator mode to a special address space, TT = $2, TM = $5 or $6. If cleared, all emulator-mode referencesare mapped into supervisor code and data spaces.14TRCIf set, the Force Emulation Mode on Trace Exception bit forces the processor to enter emulator mode when atrace exception occurs.13EMUIf set, the Force Emulation Mode bit forces the processor to begin execution in emulator mode. Refer toSection 20.4.1.1, “Emulator Mode.”12–11DDCThe 2-bit Debug Data Control field provides configuration control for capturing operand data for display on theDDATA port. The encoding is:00 No operand data is displayed01 Capture all M-Bus write data10 Capture all M-Bus read data11 Capture all M-Bus read and write dataIn all cases, the DDATA port displays the number of bytes defined by the operand reference size. For example,byte displays 8 bits, word displays 16 bits, and long displays 32 bits (one nibble at a time across multiple clockcycles.) Refer to Section 20.2.1.7, “Begin Data Transfer (PST = $8–$B).”10UHEThe User Halt Enable bit selects the CPU privilege level required to execute the HALT instruction.0 HALT is a privileged, supervisor-only instruction1 HALT is a non-privileged, supervisor/user instruction9–8BTBThe 2-bit Branch Target Bytes field defines the number of bytes of branch target address to be displayed onthe DDATA outputs. The encoding is:00 0 bytes01 Lower two bytes of the target address10 Lower three bytes of the target address11 Entire four-byte target addressRefer to Section 20.2.1.5, “Begin Execution of Taken Branch (PST = $5).”6NPLIf set, the Non-Pipelined Mode bit forces the processor core to operate in a nonpipeline mode of operation. Inthis mode, the processor effectively executes a single instruction at a time with no overlap.When operating in non-pipelined mode, performance is severely degraded. For the V3 design, operation inthis mode essentially adds 6 cycles to the execution time of each instruction. Given that the measuredEffective Cycles per Instruction for V3 is ~2 cycles/instruction, meaning performance in non-pipeline modewould be ~8 cycles/instruction, or approximately 25% compared to the pipelined performance.Regardless of the state of CSR[6], if a PC breakpoint is triggered, it is always reported before the instructionwith the breakpoint is executed. The occurrence of an address and/or data breakpoint trigger is imprecise innormal pipeline operation. When operating in non-pipeline mode, these triggers are always reported beforethe next instruction begins execution. In this mode, the trigger reporting can be considered to be precise.As previously detailed, the occurrence of an address and/or data breakpoint should always happen before thenext instruction begins execution. Therefore the occurrence of the address/data breakpoints should beguaranteed.Table 20-22. Configuration/Status Register (CSR) Field Descriptions (continued)Field Description
