Universal Serial Bus InterfaceMCF5253 Reference Manual, Rev. 124-32 Freescale Semiconductor11–10LSLine Status. These bits reflect the current logical levels of the USB D+ (bit 11) and D– (bit 10) signal lines. The use ofline status by the host controller driver is not necessary (unlike EHCI), because the connection of FS and LS ismanaged by the hardware.00 SE001 J-state10 K-state11 Undefined9 Reserved.8PRPort Reset.In host mode, when the software writes a one to this bit the bus-reset sequence as defined in the USB SpecificationRevision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior isdifferent from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timedin the driver.For the USB OTG module in device mode, this bit is a read only status bit. Device reset from the USB bus is alsoindicated in the USBSTS register.1 Port is in Reset.0 Port is not in Reset.This field is zero if Port Power(PP) is zero.7SUSPSuspendIn host mode:The Port Enabled bit (PE) and Suspend (SUSP) bit define the port states as follows:0x Disable10 Enable11 SuspendWhen in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blockingoccurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspendstate, the port is sensitive to resume detection.Note: The bit status does not change until the port is suspended and that there may be a delay in suspending a port ifthere is a transaction currently in progress on the USB.The module unconditionally sets this bit to zero when the software sets the Force Port Resume bit to zero. A write ofzero to this bit is ignored by the host controller. If the host software sets this bit to a one when the port is not enabled(that is, Port enabled bit is a zero) the results are undefined.This field is zero if Port Power(PP) is zero in host mode.For device mode:1 Port in suspend state.0 Port not in suspend state. Default.In device mode this bit is a read only status bit.Table 24-27. Port Status and Control (PORTSC) Register Field Descriptions (continued)Field Description
