NXP Semiconductors MCF5253 Reference Manual Manual pdf 443 page image
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NXP Semiconductors MCF5253 Reference Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. MCF5253 Reference Manual,
  25. about this book
  26. revision history
  27. register summary
  28. MCF5253 Overview
  29. MCF5253 Block Diagram
  30. MCF5253 Feature Details
  31. MCF5253 Functional Overview
  32. Instruction Cache
  33. ATA Controller
  34. CD-ROM Encoder/Decoder
  35. Timer Module
  36. GPIO Interface
  37. Sleep and Wake-Up Modes
  38. Overview
  39. GPIO
  40. Read-Write Control
  41. Chip Selects
  42. Serial Module Signals
  43. Digital Audio Interface Signals
  44. Subcode Interface
  45. Queued Serial Peripheral Interface (QSPI)
  46. USB Controller
  47. Test Mode
  48. BDM/JTAG Signals
  49. On-Chip Linear Regulator
  50. Processor Pipelines
  51. ColdFire Processor Memory Map and Register Definitions
  52. Address Registers (A0–A6)
  53. Description
  54. Supervisor Memory Map and Register Description
  55. Vector Base Register (VBR)
  56. Exception Stack Frame Definition
  57. Processor Exceptions
  58. Address Error Exception
  59. Debug Interrupt
  60. Fault-on-Fault Halt
  61. MOVE Instruction Execution Times
  62. Standard One Operand Instruction Execution Times
  63. Miscellaneous Instruction Execution Times
  64. Branch Instruction Execution Times
  65. PLL Features
  66. PLL Memory Map and Register Definitions
  67. PLL Operation
  68. Dynamic Clock Switching
  69. Reduced Power Mode
  70. Enter Sleep Mode
  71. Instruction Cache Features
  72. Instruction Cache Physical Organization
  73. Memory Reference Attributes
  74. Instruction Cache Memory Map and Register Definitions
  75. Instruction Cache Register
  76. Access Control Registers
  77. SRAM Features
  78. SRAM Initialization
  79. SDRAM Features
  80. Synchronous Operation
  81. DRAM Controller Signals in Synchronous Mode
  82. DRAM Controller Registers
  83. DRAM Address and Control (DACR0) (Synchronous Mode)
  84. DRAM Controller Mask Registers (DMR0)
  85. General Synchronous Operation Guidelines
  86. Interfacing Example
  87. Continuous Page Mode
  88. Auto-Refresh Operation
  89. Self-Refresh Operation
  90. Initialization Sequence
  91. SDRAM Example
  92. SDRAM Interface Configuration
  93. DACR Initialization
  94. DMR Initialization
  95. Mode Register Initialization
  96. Initialization Code
  97. Bus Features
  98. Address Bus
  100. Reset In
  101. Bus Cycle Execution
  102. Read Cycle
  103. Write Cycle
  104. Back-to-Back Bus Cycles
  105. Burst Cycles
  106. Misaligned Operands
  107. Reset Operation
  108. Software Watchdog Reset
  109. SIM Overview
  110. SIM Register Memory Map
  111. SIM Module Programming Registers
  112. Device ID Register
  113. Primary Interrupt Controller Registers
  114. Interrupt Mask Register
  115. Secondary Interrupt Controller Registers
  116. Interrupt Level Selection
  117. Spurious Vector Register
  118. Software Interrupts
  119. System Protection and Reset Status Registers
  120. System Protection Control Register
  121. Software Watchdog Interrupt Vector Register
  122. Software Watchdog Service Register
  123. Internal Arbitration Operation
  124. PARK Register Bit Configuration
  125. General Purpose I/Os
  126. General Purpose Inputs
  127. General Purpose Input Interrupts
  128. General Purpose Outputs
  129. Multiplexed Pin Configuration
  130. Chip Select Features
  131. CS1/QSPI_CS3/GPIO28
  132. Chip Select Operation
  133. Global Chip-Select Operation
  134. Chip Select Module Registers
  135. Chip Select Mask Register
  136. Chip Select Control Register
  137. Code Example
  138. Timer Module Overview
  139. Timer Signal Output
  140. Configuring the Timer for Output Mode (TIMER0)
  141. Timer Reference Registers (TRR0, TRR1)
  142. Timer Counters (TCN0, TCN1)
  143. Timer Initialization Example Code
  145. ADC Memory Map and Register Definitions
  146. AD Value Register (ADvalue)
  147. Functional Description
  148. IDE and SmartMedia Overview
  149. Buffer Enables BUFENB1, BUFENB2, and Associated Logic
  150. Generation of IDE_DIOR and IDE_DIOW
  151. Cycle Termination on CS2 (IDE_DIOR, IDE_DIOW)
  152. SmartMedia Interface Setup
  153. SmartMedia Timing
  154. Setting Up The IDE Interface
  155. IDE Timing Diagram
  156. Flash Media Interface
  157. Flash Media Interface Memory Map and Register Definitions
  158. Flash Media Interface Operation
  159. Flash Media Command Registers in Memory Stick Mode
  160. Flash Media Command Register 2 in Secure Digital Mode
  161. Flash Media Data Registers
  162. Flash Media Status Register
  163. Flash Media Interface Operation in Memory Stick Mode
  164. Reading Data from the Memory Stick
  165. Writing Data to the Memory Stick
  166. Interrupt from Memory Stick
  167. Send Command to Card
  168. Write Data to Card
  169. Commonly Used Commands in SD Mode
  170. Send Command to Card (Receive Multiple Data Blocks and Status)
  171. Send Command to Card (Write Multiple Data Blocks)
  172. DMA Features
  173. DMA Request
  174. DMA Module Overview
  175. DMA Memory Map and Register Definitions
  176. Source Address Register
  177. Destination Address Register
  178. Byte Count Register
  179. DMA Control Register
  180. DMA Status Register
  181. DMA Interrupt Vector Register
  182. Transfer Request Generation
  183. Dual-Address Write
  184. Channel Prioritization
  185. Data Transfer
  186. Channel Termination
  187. UART Module Features
  188. Serial Communication Channel
  189. UART Module Signal Definitions
  190. Request-To-Send
  191. Baud-Rate Generator/Timer
  192. Transmitter
  193. Receiver
  194. Receiver FIFO
  195. Looping Modes
  196. Local Loopback Mode
  197. Multidrop Mode
  198. Bus Operation
  199. Mode Register 1 (UMR1n)
  200. Mode Register 2 (UMR2n)
  201. Status Registers (USRn)
  202. Clock-Select Registers (USCRn)
  203. Command Registers (UCRn)
  204. Reset Transmitter
  205. Transmitter Enable
  206. Receiver Buffer Registers (UBRn)
  207. Input Port Change Registers (UIPCRn)
  208. Interrupt Status Registers (UISRn)
  209. Interrupt Mask Registers (UIMRn)
  210. Baud Rate Generator (MSB) Register (UBG1n)
  211. Output Port Data Registers (UOP1n)
  212. Programming
  213. UART Module Initialization Sequence
  214. Features
  215. Internal Bus Interface
  216. QSPI RAM
  217. Transmit RAM
  218. Baud Rate Selection
  219. Transfer Length
  220. QSPI Memory Map and Register Definitions
  221. QSPI Delay Register (QDLYR)
  222. QSPI Interrupt Register (QIR)
  223. QSPI Address Register (QAR)
  224. Command RAM Registers (QCR0–QCR15)
  225. Programming Example
  226. Audio Interface Overview
  227. Audio Interface Block Diagram
  228. Audio Interface Structure
  229. Audio Interface Memory Map and Register Definitions
  230. Audio Interrupt Mask and Status Register Descriptions
  231. IIS/EIAJ Transmitter Descriptions
  232. IIS/EIAJ Transmitter Interrupts
  233. Digital Audio Interface (EBU/SPDIF) Register Descriptions
  234. IEC958 Receive Interface
  235. Control Channel Interrupt (IEC958 "C" Channel New Frame)
  236. EBU Extracted Clock
  237. U and Q Receive Register Interrupts
  238. Behavior of User Channel Receive Interface (non-CD data)
  239. Transmit "C" Channel
  240. CD Subcode Interrupts
  241. Free Running Counter Synchronization
  242. Data Exchange Register Descriptions
  243. Data Exchange Register Overview
  244. Data In Selection
  245. PDIR and PDOR Field Formatting
  246. Overrun and Underrun with PDIR and PDOR Registers
  247. audioGlob Register Descriptions
  248. Audio Interrupts
  249. PDOR1, PDOR2, and PDOR3 Interrupts
  250. Audio Interrupt Routines and Timing
  251. CD-ROM Block Encoder and Decoder Register Descriptions
  252. CD-ROM Decoder Interrupts
  253. CD-ROM Encoder Interrupts
  254. Phase/Frequency Determination and XTRIM Function
  255. Filtering for the Discrete Time Oscillator
  256. XTRIM Internal Logic
  257. START Signal
  258. Repeated START Signal
  259. Handshaking
  261. Generation of START
  262. Post-Transfer Software Response
  263. Generation of Repeated START
  264. Arbitration Lost
  266. Boot ROM Operation
  267. Boot Type Detection
  268. Serial Boot Data Format
  269. Supported Commands
  270. Boot from UART
  271. Creating Appropriate Boot Record Files
  272. Debug Support Signals
  273. Breakpoint (BKPT)
  274. Processor Status Clock (PSTCLK)
  275. Processor Status Signal Encoding
  276. Begin Execution of Taken Branch (PST = )
  277. Begin Execution of RTE Instruction (PST = )
  278. CPU Halt
  279. BDM Serial Interface
  280. Receive Packet Format
  281. BDM Command Set
  282. Command Sequence Diagram
  283. Command Set Descriptions
  284. Write Address/Data Register (WAREG and WDREG)
  285. Write Memory Location (WRITE)
  286. Dump Memory Block (DUMP)
  287. Fill Memory Block (FILL)
  288. Resume Execution (GO)
  289. Read Control Register (RCREG)
  290. Write Control Register (WCREG)
  291. Read Debug Module Register (RDMREG)
  292. Unassigned Opcodes
  293. Real-Time Debug Support
  294. Theory of Operation
  295. Emulator Mode
  296. Debug Module Hardware
  297. Address Breakpoint Registers
  298. Address Attribute Trigger Register
  299. Program Counter Breakpoint Register (PBR, PBMR)
  300. Data Breakpoint Registers (DBR, DBMR)
  301. Trigger Definition Register (TDR)
  302. Configuration/Status Register (CSR)
  303. BDM Address Attribute Register (BAAR)
  304. Freescale-Recommended BDM Pinout
  306. JTAG Signal Descriptions
  307. Test Clock (TCK)
  308. Test Data Input/Development Serial Input (TDI/DSI)
  309. JTAG Register Definitions
  310. SAMPLE/PRELOAD Instruction
  311. BYPASS Instruction
  312. JTAG Boundary Scan Register
  313. Obtaining the IEEE 1149.1A Standard
  314. Introduction
  315. ATA DMA Address Register (ATA_DADDR)
  316. USB/FlexCAN Clock Register (USBCANCLK)
  317. Endianness Issues
  320. Modes of Operation
  321. External Signal Description
  322. ATA_DIOR (Out)
  323. Timing on ATA Bus
  324. PIO Mode Timing
  325. Timing in Multiword DMA Mode
  326. UDMA In Timing Diagrams
  327. UDMA Out Timing Diagrams
  328. Memory Map and Register Definitions
  329. Memory Map
  330. Register Descriptions
  331. Timing Registers
  332. TIME_1 Register
  333. TIME_AX Register
  334. TIME_M Register
  335. TIME_K Register
  336. TIME_ZAH Register
  337. TIME_DZFS Register
  338. TIME_CYC Register
  339. FIFO_FILL Register
  340. Interrupt Registers
  341. Interrupt_Pending Register
  342. Interrupt_Enable Register
  343. Interrupt_Clear Register
  344. Drive Registers Connected to ATA Bus
  345. Resetting ATA Bus
  346. Using DMA Mode to Receive Data from ATA Bus
  347. Using DMA Mode to Transmit Data to ATA Bus
  349. Block Diagram
  351. System Clock
  352. Module Identification Registers
  353. General Hardware Parameters (HWGENERAL) Register
  354. Host Hardware Parameters (HWHOST) Register
  355. Transmit Buffer Hardware Parameters (HWTXBUF) Register
  356. Receive Buffer Hardware Parameters (HWRXBUF) Register
  357. Capability Registers
  358. Host Controller Structural Parameters (HCSPARAMS)
  359. Device Controller Interface Version (DCIVERSION)
  360. Operational Registers
  361. USB Status Register (USBSTS)
  362. USB Interrupt Enable Register (USBINTR)
  363. Frame Index Register (FRINDEX)
  364. Control Data Structure Segment Register (CTRLDSSEGMENT)
  365. Device Address Register (DEVICEADDR), Non-EHCI
  366. Endpoint List Address Register (ENDPOINTLISTADDR), Non-EHCI
  367. Master Interface Data Burst Size Register (BURSTSIZE)—Non-EHCI
  368. Transmit FIFO Tuning Controls Register (TXFILLTUNING)—Non-EHCI
  369. Configure Flag Register (CONFIGFLAG)
  370. On-The-Go Status and Control (OTGSC), Non-EHCI
  371. USB Mode Register (USBMODE)—Non-EHCI
  372. Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI
  373. Endpoint Initialization Register (ENDPTPRIME)—Non-EHCI
  374. Endpoint Flush Register (ENDPTFLUSH), Non-EHCI
  375. Endpoint Status Register (ENDPTSTATUS), Non-EHCI
  376. Endpoint Complete Register (ENDPTCOMPLETE), Non-EHCI
  377. Endpoint Control Register n (ENDPTCTRLn), Non-EHCI
  379. FIFO RAM Controller
  380. Periodic Frame List
  381. Asynchronous List Queue Head Pointer
  382. Isochronous (High-Speed) Transfer Descriptor (iTD)
  383. iTD Transaction Status and Control List
  384. iTD Buffer Page Pointer List (Plus)
  385. Split Transaction Isochronous Transfer Descriptor (siTD)
  386. siTD Endpoint Capabilities/Characteristics
  387. siTD Transfer State
  388. siTD Buffer Pointer List (Plus)
  389. siTD Back Link Pointer
  390. Next qTD Pointer
  391. qTD Token
  392. qTD Buffer Page Pointer List
  393. Queue Head Horizontal Link Pointer
  394. Transfer Overlay
  395. Periodic Frame Span Traversal Node (FSTN)
  396. FTSN Normal Path Pointer
  397. Host Controller Initialization
  398. Power Port
  399. Port Suspend/Resume
  400. Schedule Traversal Rules
  401. Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries
  402. Periodic Schedule
  403. Managing Isochronous Transfers Using iTDs
  404. Software Operational Model for iTDs
  405. Periodic Scheduling Threshold
  406. Asynchronous Schedule
  407. Adding Queue Heads to Asynchronous Schedule
  408. Removing Queue Heads from Asynchronous Schedule
  409. Empty Asynchronous Schedule Detection
  410. Asynchronous Schedule Traversal: Start Event
  411. Buffer Pointer List Use for Data Streaming with qTDs
  412. Adding Interrupt Queue Heads to the Periodic Schedule
  413. Ping Control
  414. Split Transactions
  415. Asynchronous—Do-Start-Split
  416. Split Transaction Interrupt
  417. Host Controller Operational Model for FSTNs
  418. Software Operational Model for FSTNs
  419. Tracking Split Transaction Progress for Interrupt Transfers
  420. Periodic Interrupt—Do-Start-Split
  421. Periodic Interrupt—Do-Complete-Split
  422. Managing the QH[FrameTag] Field
  423. Rebalancing the Periodic Schedule
  424. Split Transaction Scheduling Mechanisms for Isochronous
  425. Tracking Split Transaction Progress for Isochronous Transfers
  426. Split Transaction Execution State Machine for Isochronous
  427. Periodic Isochronous—Do Complete Split
  428. Complete-Split for Scheduling Boundary Cases 2a, 2b
  429. Split Transaction for Isochronous—Processing Examples
  430. Port Test Modes
  431. Interrupts
  432. Transfer/Transaction Based Interrupts
  433. Data Buffer Error
  434. USB Interrupt (Interrupt on Completion (IOC))
  435. Host System Error
  436. Endpoint Queue Head
  437. Endpoint Capabilities/Characteristics
  439. Endpoint Transfer Descriptor (dTD)
  440. Device Operational Model
  441. Port State and Control
  442. Bus Reset
  443. Suspend/Resume
  444. Managing Endpoints
  445. Stalling
  446. Data Toggle Inhibit
  447. Priming Receive Endpoints
  448. Interrupt/Bulk Endpoint Bus Response Matrix
  449. Control Endpoint Operation Model
  450. Status Phase
  451. Isochronous Endpoint Operational Model
  452. Isochronous Pipe Synchronization
  453. Managing Queue Heads
  454. Queue Head Initialization
  455. Operational Model For Setup Transfers
  456. Building a Transfer Descriptor
  457. Transfer Completion
  458. Flushing/De-Priming an Endpoint
  459. Servicing Interrupts
  460. Deviations from the EHCI Specifications
  461. Discovery
  462. Operational Model
  463. Asynchronous Transaction Scheduling and Buffer Management
  464. Multiple Transaction Translators
  465. Embedded Design
  466. Port Speed Detection
  469. The CAN System
  470. Module Disabled Mode
  471. Listen-only Mode
  472. FlexCAN Configuration Register (CANMCRn)
  473. FlexCAN Control Register (CANCTRLn)
  474. FlexCAN Free Running Timer Register (TIMERn)
  475. FlexCAN Error Counter Register (ERRCNTn)
  476. FlexCAN Error and Status Register (ERRSTATn)
  477. Interrupt Mask Register (IMASKn)
  478. Message Buffer Structure
  479. Functional Overview
  480. Arbitration Process
  481. Self-Received Frames
  482. Matching Process
  483. Locking and Releasing Message Buffers
  484. CAN Protocol Related Frames
  485. Time Stamp
  486. FlexCAN Initialization Sequence
  489. Miscellaneous Configuration Register (MISCCR)
NXP Semiconductors MCF5253 Reference Manual Manual pdf 443 page image
Advanced Technology Attachment Controller (ATA)MCF5253 Reference Manual, Rev. 1Freescale Semiconductor 23-17MBAR2 + 0x802 (TIME_1) R TIME_1[7:0]WMBAR2 + 0x803 (TIME_2W) R TIME_2W[7:0]WMBAR2 + 0x804 (TIME_2R) R TIME_2R[7:0]WMBAR2 + 0x805 (TIME_AX) R TIME_AX[7:0]WMBAR2 + 0x80F (TIME_PIO_RDX) R TIME_RDX[7:0]WMBAR2 + 0x807 (TIME_4) R TIME_4[7:0]WMBAR2 + 0x808 (TIME_9) R TIME_9[7:0]WMBAR2 + 0x809 (TIME_M) R TIME_M[7:0]WAddress R TIME_JN[7:0]WAddress R TIME_D[7:0]WAddress R TIME_K[7:0]WMBAR2 + 0x80D (TIME_ACK) R TIME_ACK[7:0]WAddress R TIME_ENV[7:0]WAddress R TIME_RPX[7:0]WAddress R TIME_ZAH[7:0]WMBAR2 + 0x811 (TIME_MLIX) R TIME_MLIX[7:0]WMBAR2 + 0x812 (TIME_DVH) R TIME_DVH[7:0]WAddress R TIME_DZFS[7:0]WAddress R TIME_DVS[7:0]WAddress R TIME_CVH[7:0]WAddress R TIME_SS[7:0]WTable 23-9. ATA Register Summary (continued)Name 7 6 5 4 3 2 1 0
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