Analog to Digital Converter (ADC)MCF5253 Reference Manual, Rev. 1Freescale Semiconductor 12-5the comparator will have difficulty determining if the result is negative or positive. The circuit becomessensitive to noise. Therefore, we recommend to set K between 20 and 50.Eqn. 12-2The ADCCLOCK should be such that the comparator can take the decision whether its output needs to bepositive or negative in time t.When K is high it means that RC is high relative to the clock period of the ADC and the voltage step overC per clock cycle becomes small. Therefore, the ADC becomes slow in responding to changes of the inputvoltage and this affects the accuracy of the measurement.For a correct measurement, the voltage over C should be equal to the input voltage during the entiremeasurement cycle (1024 ADC clocks). Therefore for the first conversion or when switching channels,two consecutive measurements should be made and the first one ignored. This then allows the capacitor(C) to charge to the average value of the channel. If voltages between the channels are significantlydifferent, the first measurement will be inaccurate because the capacitor may not have charged to the newlevel in time. When reading the same channel, it is not necessary to ignore every other measurement.We therefore recommend to use R = 33kΩ, C = 10nF with ADCLK = BUSCLK/256. This should producegood results for typical system clock frequencies between 30 MHz and 70 MHz.t 1ADCCLOCK-----------------------------------=
