Synchronous DRAM Controller ModuleMCF5253 Reference Manual, Rev. 1Freescale Semiconductor 7-9It is important to ensure that the Command (CBM) or AP control signal is connected to correct Addressline on the selected SDRAM. The address line used (or position) for the AP control signal is programmablevia bits 10:8 of the DACRx register.In the case of a Samsung SDRAM (K4S641633D-G) which has 8 column address lines the AP address pinis A10 (the address line used for the CBM/AP control signal may differ on other manufacturer devices).We choose to use A19 for the CBM/AP control signal and connect it to A10 on the SDRAM. We then setDACRx bits 10:8 to 010b which selects A19 as the CBM/AP mapping the Bank Select pins above this.Note: for SDRAM’s with more column address lines the position of the CBM / AP control signal movesup one address line in each case.The following SDRAM pin connection tables are for use with 4Mbit, 16Mbit, 64Mbit or 128Mbit devicesonly.)The following SDRAM pin connection tables are for use with 256 Mbit devices only.For the 256 Mbyte SDRAM, there is the restriction that address line A20 cannot be output. (we need A24).If you want consistent mapping of the D-RAM in ColdFire memory space, A20 must be sent to theD-RAM. To get this done, the only way is to make sure the D-RAM controller outputs A20 during the CASphase on A21, and ensure address pin A21 is connected to a D-RAM pin that uses both row and columnaddress. In this case, there is only one such pin, and this is A8 (CAS8/RAS8). Also, to get the columnaddress on A21, the AP bit must be set above this, lowest we can set it is A22. So, AP must be connectedto A22. Bank addresses are then A23 and above. (Bank addresses need equal address during CAS and RASphase). The remaining 3 D-RAM ras-only address lines are connected to A9, A11 and A12.Table 7-7. SDRAM Interface (16-Bit Port, 8-Column Address Lines)MCF5253 Pins A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23Row 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23Column 1 2 3 4 5 6 7 8 – – – – – – –SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14Table 7-8. SDRAM Interface (16-Bit Port, 9-Column Address Lines)MCF5253 Pins A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23Row 16 15 14 13 12 11 10 9 18 19 20 21 22 23Column 1 2 3 4 5 6 7 8 17 – – – – –SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13Table 7-9. SDRAM Interface (16-Bit Port, 10-Column Address LinesMCF5253 Pins A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A21 A22 A23Row 16 15 14 13 12 11 10 9 18 20 21 22 23Column 1 2 3 4 5 6 7 8 17 19 – – –SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
