NXP Semiconductors freescale K51 Series Reference Manual

LPTMRx_CSR field descriptions (continued)Field DescriptionThe Timer Pin Polarity configures the polarity of the input source in Pulse Counter mode. The Timer PinPolarity should only be changed when the LPTMR is disabled.0 Pulse Counter input source is active high, and LPTMR Counter Register will increment on the risingedge.1 Pulse Counter input source is active low, and LPTMR Counter Register will increment on the fallingedge.2TFCTimer Free Running CounterWhen clear the Timer Free Running Counter configures the LPTMR Counter Register to reset wheneverthe Timer Compare Flag is set. When set, the Timer Free Running Counter configures the LPTMRCounter Register to reset on overflow. The Timer Free Running Counter should only be altered when theLPTMR is disabled.0 LPTMR Counter Register is reset whenever the Timer Compare Flag is set.1 LPTMR Counter Register is reset on overflow.1TMSTimer Mode SelectThe Timer Mode Select configures the mode of the LPTMR. The Timer Mode Select should only bealtered when the LPTMR is disabled.0 Time Counter mode.1 Pulse Counter mode.0TENTimer EnableWhen the Timer Enable bit is clear, it resets the LPTMR internal logic (including the LPTMR CounterRegister and Timer Compare Flag). When the Timer Enable bit is set, the LPTMR is enabled. Whenwriting 1 to this bit, bits LPTMR_CSR[5:1] should not be altered.0 LPTMR is disabled and internal logic is reset.1 LPTMR is enabled.40.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)Addresses: LPTMR0_PSR is 4004_0000h base + 4h offset = 4004_0004hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0PRESCALEPBYPPCSWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LPTMRx_PSR field descriptionsField Description31–7ReservedThis read-only field is reserved and always has the value zero.Table continues on the next page...Chapter 40 Low power timer (LPTMR)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1001