NXP Semiconductors freescale K51 Series Reference Manual

Table 50-53. Data alignment (continued)24-bit lsb aligned 23:024-bit msb aligned 23:0In addition, if lsb alignment is selected, the receive data can be zero-extended or sign-extended.• In zero-extension, all bits above the most significant bit are 0s. This format is usefulwhen data is stored in a pure integer format.• In sign-extension, all bits above the most significant bit are equal to the mostsignificant bit. This format is useful when data is stored in a fixed-point integerformat (which implies fractional values).The RCR[RXEXT] bit controls receive data extension. Transmit data used with lsbalignment has no concept of sign/zero-extension. Unused bits above the most significantbit are simply ignored.When configured in I2S or AC97 mode, the I2S forces the selection of lsb alignment.However, RXEXT chooses zero-extension and sign-extension.50.4.4 Receive interrupt enable bit descriptionIf the receive FIFO is not enabled and the IER[RIE] and CR[RE] bits are set:• an interrupt occurs when the corresponding I2S receive data ready (ISR[RDR0/1]) bitis set• one value can be read from the RX register (one each in two-channel mode)If the receive FIFO is enabled and the IER[RIE] and CR[RE] bits are set:• an interrupt occurs when either of the I2S receive FIFO full (ISR[RFF0/1) bits is set• a maximum of 15 values are available to be read (15 values per channel in two-channel mode)If the IER[RIE] bit is cleared, these interrupts are disabled. However, the RFF0/1 andRDR0/1 bits indicate the receive data register full condition. Reading the RX registersclears the ISR[RDR] bits, thus clearing the pending interrupt. Two receive data interrupts(two per channel in two-channel mode) are available: receive data with exception statusand receive data without exception. The following table shows the conditions underwhich these interrupts are generated.Functional descriptionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111476 Freescale Semiconductor, Inc.