NXP Semiconductors freescale K51 Series Reference Manual

37.4.2 PDB Trigger Input Source SelectionThe PDB has up to 15 trigger input sources, namely Trigger-In 0 to 14. They areconnected to on-chip or off-chip event sources. The PDB can be triggered by softwarethrough the SC[SWTRIG]. SC[TRIGSEL] bits select the active trigger input source orsoftware trigger.For the trigger input sources implemented in this MCU, refer to Chip Configurationinformation.37.4.3 DAC Interval Trigger OutputsPDB can generate the interval triggers for DACs to update their outputs periodically.DAC interval counter x is reset and started when a trigger input event occurs ifDACINTCx[EXT] is cleared. When the interval counter x is equal to the value set inDACINTx register, the DAC interval trigger x output generates a pulse of one peripheralclock cycle width to update the DACx. If DACINTCx[EXT] is set, the DAC intervalcounter is bypassed and the interval trigger output x generates a pulse following thedetection of a rising edge on the DAC external trigger input. The counter and intervaltrigger can be disabled by clearing the DACINTCx[TOE].DAC interval counters are also reset when the PDB counter reaches the MOD registervalue, therefore when the PDB counter rolls over to zero, the DAC interval countersstarts anew.Together, the DAC interval trigger pulse and the ADC pre-trigger/trigger pulses allowprecise timing of DAC updates and ADC measurements. This is outlined in the typicaluse case described in the following diagram.Functional DescriptionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011846 Freescale Semiconductor, Inc.