NXP Semiconductors freescale K51 Series Reference Manual

Address: EWM_CTRL is 4006_1000h base + 0h offset = 4006_1000hBit 7 6 5 4 3 2 1 0Read 0 INEN ASSIN EWMENWriteReset 0 0 0 0 0 0 0 0EWM_CTRL field descriptionsField Description7–3ReservedThis read-only field is reserved and always has the value zero.2INENInput Enable.This bit when set, enables the EWM_in port.1ASSINEWM_in's Assertion State Select.Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit inverts the assert state to a logicone.0EWMENEWM enable.This bit when set, enables the EWM module. This resets the EWM counter to zero and deasserts theEWM_out signal. Clearing EWMEN bit disables the EWM, and therefore it cannot be enabled until a resetoccurs, due to the write-once nature of this bit.22.3.2 Service Register (EWM_SERV)The SERV register provides the interface from the CPU to the EWM module. It is write-only and reads of this register return zero.Address: EWM_SERV is 4006_1000h base + 1h offset = 4006_1001hBit 7 6 5 4 3 2 1 0Read 0Write SERVICEReset 0 0 0 0 0 0 0 0EWM_SERV field descriptionsField Description7–0SERVICEThe EWM service mechanism requires the CPU to write two values to the SERV register: a first data byteof 0xB4, followed by a second data byte of 0x2C. The EWM service is illegal if either of the followingconditions is true.• The first or second data byte is not written correctly.• The second data byte is not written within a fixed number of peripheral bus cycles of the first databyte. This fixed number of cycles is called EWM_service_time.Chapter 22 External Watchdog Monitor (EWM)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 497