NXP Semiconductors freescale K51 Series Reference Manual

31.4.5.6 Conversion time examplesThe following examples use Figure 31-95 and the information provided in Table 31-107through Table 31-111.31.4.5.6.1 Typical conversion time configurationA typical configuration for ADC conversion is: 10-bit mode, with the bus clock selectedas the input clock source, the input clock divide-by-1 ratio selected, and a bus frequencyof 8 MHz, long sample time disabled and high speed conversion disabled. Theconversion time for a single conversion is calculated by using Figure 31-95 and theinformation provided in Table 31-107 through Table 31-111. The table below list thevariables of Figure 31-95.Table 31-112. Typical conversion timeVariable TimeSFCAdder 5 ADCK cycles + 5 bus clock cyclesAverageNum 1BCT 20 ADCK cyclesLSTAdder 0HSCAdder 0The resulting conversion time is generated using the parameters listed in the proceedingtable. Therefore, for a bus clock equal to 8 MHz and an ADCK equal to 8 MHz theresulting conversion time is 3.75 μs.31.4.5.6.2 Long conversion time configurationA configuration for long ADC conversion is: 16-bit differential mode with the bus clockselected as the input clock source, the input clock divide-by-8 ratio selected, a busfrequency of 8 MHz, long sample time enabled, configured for longest adder, high speedconversion disabled, and average enabled for 32 conversions. The conversion time forthis conversion is calculated by using Figure 31-95 and the information provided in Table31-107 through Table 31-111. The following table lists the variables of the Figure 31-95.Table 31-113. Typical conversion timeVariable TimeSFCAdder 3 ADCK cycles + 5 bus clock cyclesAverageNum 32BCT 34 ADCK cyclesLSTAdder 20 ADCK cyclesTable continues on the next page...Functional descriptionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011740 Freescale Semiconductor, Inc.