NXP Semiconductors freescale K51 Series Reference Manual

• The MCU is reset or enters Low Power Stop modes.• The MCU enters Normal Stop mode with ADACK not enabled.When a conversion is aborted, the contents of the data registers, Rn, are not altered. Thedata registers continue to be the values transferred after the completion of the lastsuccessful conversion. If the conversion was aborted by a reset or Low Power Stopmodes, RA and R n return to their reset states.31.4.5.4 Power controlThe ADC module remains in its idle state until a conversion is initiated. If ADACK isselected as the conversion clock source, but the asynchronous clock output is disabled(ADACKEN=0), the ADACK clock generator also remains in its idle state (disabled)until a conversion is initiated. If the asynchronous clock output is enabled(ADACKEN=1), it remains active regardless of the state of the ADC or the MCU powermode.Power consumption when the ADC is active can be reduced by setting ADLPC. Thisresults in a lower maximum value for fADCK .31.4.5.5 Sample time and total conversion timeFor short sample (ADLSMP=0), there is a 2-cycle adder for first conversion over the basesample time of 4 ADCK cycles. For high speed conversions (ADHSC=1), there is anadditional 2-cycle adder on any conversion. The table below summarizes sample timesfor the possible ADC configurations.ADC Configuration Sample time (ADCK cycles)ADLSMP ADLSTS ADHSC First or Single Subsequent0 X 0 6 41 00 0 241 01 0 161 10 0 101 11 0 60 X 1 8 61 00 1 261 01 1 181 10 1 12Table continues on the next page...Chapter 31 Analog-to-Digital Converter (ADC)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 737