NXP Semiconductors freescale K51 Series Reference Manual

PORT memory map (continued)Absoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 32 w1c 0000_0000h 11.4.4/2494004_D0C0 Digital Filter Enable Register (PORTE_DFER) 32 R/W 0000_0000h 11.4.5/2504004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 32 R/W 0000_0000h 11.4.6/2514004_D0C8 Digital Filter Width Register (PORTE_DFWR) 32 R/W 0000_0000h 11.4.7/25111.4.1 Pin Control Register n (PORTx_PCRn)For PCR1 to PCR5 of the port A, bit 0, 1, 6, 8, 9,10 reset to 1; for the PCR0 of the portA, bit 1, 6, 8, 9, 10 reset to 1; in other conditions, all bits reset to 0.Addresses: 4004_9000h base + 0h offset + (4d × n), where n = 0d to 31dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0ISF0 IRQCLK 0 MUX 0DSEODEPFE 0SREPEPSW w1cReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PORTx_PCRn field descriptionsField Description31–25ReservedThis read-only field is reserved and always has the value zero.24ISFInterrupt Status FlagThe pin interrupt configuration is valid in all digital pin muxing modes.0 Configured interrupt has not been detected.1 Configured interrupt has been detected. If pin is configured to generate a DMA request then thecorresponding flag will be cleared automatically at the completion of the requested DMA transfer,otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitiveinterrupt that remains asserted then flag will set again immediately.23–20ReservedThis read-only field is reserved and always has the value zero.19–16IRQCInterrupt ConfigurationThe pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configuredto generate interrupt / DMA Request as follows:0000 Interrupt/DMA Request disabled.0001 DMA Request on rising edge.0010 DMA Request on falling edge.0011 DMA Request on either edge.0100 Reserved.1000 Interrupt when logic zero.Table continues on the next page...Memory map and register definitionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011246 Freescale Semiconductor, Inc.