NXP Semiconductors freescale K51 Series Reference Manual

I2Sx_CR field descriptions (continued)Field DescriptionThis bit provides the option to keep the frame-sync and clock enabled or to disable them after the receiveframe in which the receiver is disabled. Writing to this bit has effect only when CR[RE] is disabled.Thereceiver is disabled by clearing the CR[RE] bit.0 Continue frame-sync/clock generation after current frame during which CR[RE] is cleared. This maybe required when Frame-sync and Clocks are required from I2S, even when no data is to be received.1 Stop frame-sync/clock generation at next frame boundary. This will be effective also in case wherereceiver is already disabled in current or previous frames.10TFRCLKDISTransmit Frame Clock Disable.This bit provide option to keep the frame-sync and clock enabled or disabled after current transmit frame,in which transmitter is disabled by clearing CR[TE] bit. Writing to this bit has effect only when I2S isenabled CR[TE] is disabled.0 Continue frame-sync/clock generation after current frame during which CR[TE] is cleared. This maybe required when frame-sync and clocks are required from I2S, even when no data is to be received.1 Stop frame-sync/clock generation at next frame boundary. This will be effective also in case wheretransmitter is already disabled in current or previous frames.9CLKISTClock Idle State.This bit controls the idle state of the transmit clock port during I2S internal gated mode. Note: When Clockidle state is `1' the clock polarity should always be negedge triggered and when clock idle = `0' the clockpolarity should always be positive edge triggered.0 Clock idle state is `0'.1 Clock idle state is `1'.8TCHENTwo-Channel Operation Enable.This bit allows I2S to operate in the two-channel mode.In this mode while receiving, the RXSR transfersdata to RX0 and RX1 alternately and while transmitting, data is alternately transferred from TX0 and TX1to TXSR. For an even number of slots, two-channel operation can be enabled to optimize usage of bothFIFOs or disabled as in the case of odd number of active slots. This feature is especially useful in I2Smode, where data for left speaker can be placed in Tx-FIFO0 and for right speaker in Tx-FIFO1.0 Two-channel mode disabled.1 Two-channel mode enabled.7SYSCLKENSystem Clock (Oversampling Clock) Enable.When set, this bit allows the I2S to output the (network clock) at the SRCK port, provided thatsynchronous mode, and transmit internal clock mode are set. The relationship between bit clock andnetwork clock is determined by DIV2, PSR, and PM bits. This feature is especially useful in I2S mastermode to output oversampling clock on SRCK port.0 Network clock not output on SRCK port.1 Network clock output on SRCK port.6–5I2SMODEI2S Mode SelectThese bits allow the I2S to operate in normal, I2S master or I2S slave mode.00 Normal mode01 I2S master modeTable continues on the next page...Memory map/register definitionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111424 Freescale Semiconductor, Inc.