NXP Semiconductors freescale K51 Series Reference Manual

33.4.2 DAC Data High Register (DACx_DATH)Addresses: 400C_C000h base + 1h offset + (2d × n), where n = 0d to 15dBit 7 6 5 4 3 2 1 0Read 0 DATA[11:8]WriteReset 0 0 0 0 0 0 0 0DACx_DATnH field descriptionsField Description7–4ReservedThis read-only field is reserved and always has the value zero.3–0DATA[11:8]When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the followingformula. Vout = Vin * (1 + DACDAT0[11:0])/4096When the DAC Buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.33.4.3 DAC Status Register (DACx_SR)If DMA is enabled, the flags can be cleared automatically by DMA when the DMArequest is done. Write zero to a bit to clear it. Writing one has no effect. After resetDACBFRPTF is set and can be cleared by software, if needed. The flags are set onlywhen the data buffer status is changed.Addresses: DAC0_SR is 400C_C000h base + 20h offset = 400C_C020hDAC1_SR is 400C_D000h base + 20h offset = 400C_D020hBit 7 6 5 4 3 2 1 0Read 0 DACBFWMF DACBFRPTF DACBFRPBFWriteReset 0 0 0 0 0 0 1 0DACx_SR field descriptionsField Description7–3ReservedThis read-only field is reserved and always has the value zero.Reserved2DACBFWMFDAC buffer watermark flag0 The DAC buffer read pointer has not reached the watermark level.1 The DAC buffer read pointer has reached the watermark level.1DACBFRPTFDAC buffer read pointer top position flagTable continues on the next page...Chapter 33 12-bit Digital-to-Analog Converter (DAC)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 795