NXP Semiconductors freescale K51 Series Reference Manual

50.4.2.1 I2S clock and frame sync generationData clock and frame sync signals can be generated internally, or can be obtained fromexternal sources. If internally generated, the I2S clock generator is used to derive bitclock and frame sync signals from the network clock . The I2S clock generator consists ofa selectable, fixed prescaler and a programmable prescaler for bit rate clock generation.In gated clock mode, the data clock is valid only when data is being transmitted.Otherwise the clock port is pulled to the inactive state. A programmable frame ratedivider and a word length divider are used for frame rate sync signal generation.The following figure shows a block diagram of the clock generator for the transmitsection. The serial bit clock can be internal or external, depending on the TCR[TXDIR]bit. The receive section contains an equivalent clock generator circuit.Prescaler(/1 or /8) Divider(/1 to /256)TXDIR(0=input)TXDIR(1=output)WL[3:0]PM[7:0]STCKTXDIRSYSCLKENDivider(/1 or /2)Divide by2Word clockTXDIR(1=output)Network clockNetwork clock (SRCK)Serial bit clockWord lengthdividerPSRDIV2Figure 50-56. I2S transmit clock generator block diagramThe following figure shows the frame sync generator block for the transmit section.When internally generated, both receive and transmit frame sync are generated from theword clock and are defined by the frame rate divider (DC) bits and the word length (WL)bits of the TCCR. The receive section contains an equivalent circuit for the frame syncgenerator.Chapter 50 Integrated interchip sound (I2S)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1471