NXP Semiconductors freescale K51 Series Reference Manual

ADCx_CFG2 field descriptions (continued)Field DescriptionADHSC configures the ADC for very high speed operation. The conversion sequence is altered (2 ADCKcycles added to the conversion time) to allow higher speed conversion clocks.0 Normal conversion sequence selected.1 High speed conversion sequence selected (2 additional ADCK cycles to total conversion time).1–0ADLSTSLong sample time selectADLSTS selects between the extended sample times when long sample time is selected (ADLSMP=1).This allows higher impedance inputs to be accurately sampled or to maximize conversion speed for lowerimpedance inputs. Longer sample times can also be used to lower overall power consumption whencontinuous conversions are enabled if high conversion rates are not required.00 Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total).01 12 extra ADCK cycles; 16 ADCK cycles total sample time.10 6 extra ADCK cycles; 10 ADCK cycles total sample time.11 2 extra ADCK cycles; 6 ADCK cycles total sample time.31.3.4 ADC data result register (ADCx_Rn)The data result registers (Rn) contain the result of an ADC conversion of the channelselected by the corresponding status and channel control register (SC1A:SC1n). Forevery status and channel control register, there is a corresponding data result register.Unused bits in the Rn register are cleared in unsigned right justified modes and carry thesign bit (MSB) in sign extended 2's complement modes. For example, when configuredfor 10-bit single-ended mode, D[15:10] are cleared. When configured for 11-bitdifferential mode, D[15:10] carry the sign bit (bit 10 extended through bit 15).The following table describes the behavior of the data result registers in the differentmodes of operation.Table 31-44. Data result register descriptionConversionmodeD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format16-bit differential S D D D D D D D D D D D D D D D Signed 2'scomplement16-bit single-endedD D D D D D D D D D D D D D D D Unsigned rightjustified13-bit differential S S S S D D D D D D D D D D D D Sign extended2's complement12-bit single-ended0 0 0 0 D D D D D D D D D D D D Unsigned rightjustifiedTable continues on the next page...Register DefinitionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011716 Freescale Semiconductor, Inc.