NXP Semiconductors freescale K51 Series Reference Manual

SPIx_MCR field descriptions (continued)Field Description13DIS_TXFDisable Transmit FIFOWhen the TX FIFO is disabled, the transmit part of the DSPI operates as a simplified double-buffered SPI.This bit can only be written when the MDIS bit is cleared.0 Tx FIFO is enabled.1 Tx FIFO is disabled.12DIS_RXFDisable Receive FIFOWhen the RX FIFO is disabled, the receive part of the DSPI operates as a simplified double-buffered SPI.This bit can only be written when the MDIS bit is cleared.0 Rx FIFO is enabled.1 Rx FIFO is disabled.11CLR_TXFClear TX FIFOFlushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The CLR_TXF bit is alwaysread as zero.0 Do not clear the Tx FIFO counter.1 Clear the Tx FIFO counter.10CLR_RXFFlushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The CLR_RXF bit is always readas zero.0 Do not clear the Rx FIFO counter.1 Clear the Rx FIFO counter.9–8SMPL_PTSample PointControls when the DSPI master samples SIN in Modified Transfer Format. This field is valid only whenCPHA bit in CTAR register is 0.00 0 system clocks between SCK edge and SIN sample01 1 system clock between SCK edge and SIN sample10 2 system clocks between SCK edge and SIN sample11 Reserved7–2ReservedThis read-only field is reserved and always has the value zero.1ReservedThis read-only field is reserved and always has the value zero.0HALTHaltStarts and stops DSPI transfers.0 Start transfers.1 Stop transfers.Chapter 46 SPI (DSPI)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1135