NXP Semiconductors freescale K51 Series Reference Manual

Addresses: FTM0_EXTTRIG is 4003_8000h base + 6Ch offset = 4003_806ChFTM1_EXTTRIG is 4003_9000h base + 6Ch offset = 4003_906ChFTM2_EXTTRIG is 400B_8000h base + 6Ch offset = 400B_806ChBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16RReserved[bit 8]WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RReserved[7:0]TRIGFINITTRIGENCH1TRIGCH0TRIGCH5TRIGCH4TRIGCH3TRIGCH2TRIGWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FTMx_EXTTRIG field descriptionsField Description31–8ReservedThis field is reserved.7TRIGFChannel Trigger FlagSet by hardware when a channel trigger is generated. Clear TRIGF by reading EXTTRIG while TRIGF isset and then writing a 0 to TRIGF. Writing a 1 to TRIGF has no effect.If another channel trigger is generated before the clearing sequence is completed, the sequence is resetso TRIGF remains set after the clear sequence is completed for the earlier TRIGF.0 No channel trigger was generated.1 A channel trigger was generated.6INITTRIGENInitialization Trigger EnableEnables the generation of the trigger when the FTM counter is equal to the CNTIN register.0 The generation of initialization trigger is disabled.1 The generation of initialization trigger is enabled.5CH1TRIGChannel 1 Trigger EnableEnable the generation of the channel trigger when the FTM counter is equal to the CnV register.0 The generation of the channel trigger is disabled.1 The generation of the channel trigger is enabled.4CH0TRIGChannel 0 Trigger EnableEnable the generation of the channel trigger when the FTM counter is equal to the CnV register.0 The generation of the channel trigger is disabled.1 The generation of the channel trigger is enabled.3CH5TRIGChannel 5 Trigger EnableTable continues on the next page...Memory Map and Register DefinitionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011888 Freescale Semiconductor, Inc.