DMA_TCDn_NBYTES_MLOFFNO field descriptions (continued)Field DescriptionAs a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriatereads and writes perform until the minor byte transfer count has transferred. This is an indivisibleoperation and cannot be halted; although, it may be stalled by using the bandwidth control field, or viapreemption. After the minor count is exhausted, the SADDR and DADDR values are written back into theTCD memory, the major iteration count is decremented and restored to the TCD memory. If the majoriteration count is completed, additional processing is performed.21.3.22 TCD Signed Minor Loop Offset (Minor Loop and OffsetEnabled) (DMA_TCD_NBYTES_MLOFFYES)TCD word 2 is defined as follows if:• Minor loop mapping is enabled (CR[EMLM] = 1) and• Minor loop offset enabled (SMLOE or DMLOE = 1)If minor loop mapping is enabled and SMLOE and DMLOE are cleared then refer to theTCD_NBYTES_MLOFFNO register description.Addresses: 4000_8000h base + 1008h offset + (32d × n), where n = 0d to 15dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RSMLOEDMLOEMLOFF NBYTESWReset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x** Notes:x = Undefined at reset.•DMA_TCDn_NBYTES_MLOFFYES field descriptionsField Description31SMLOESource Minor Loop Offset EnableSelects whether the minor loop offset is applied to the source address upon minor loop completion.0 The minor loop offset is not applied to the SADDR1 The minor loop offset is applied to the SADDR30DMLOEDestination Minor Loop Offset enableSelects whether the minor loop offset is applied to the destination address upon minor loop completion.0 The minor loop offset is not applied to the DADDR1 The minor loop offset is applied to the DADDR29–10MLOFFIf SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source ordestination address to form the next-state value after the minor loop completes.Table continues on the next page...Chapter 21 Direct Memory Access Controller (eDMA)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 461