NXP Semiconductors freescale K51 Series Reference Manual

Section Number Title Page21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................44321.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................44421.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................44521.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................44621.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................44721.3.11 Clear Error Register (DMA_CERR)............................................................................................................44821.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................44921.3.13 Interrupt Request Register (DMA_INT)......................................................................................................44921.3.14 Error Register (DMA_ERR)........................................................................................................................45221.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................45421.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................45621.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................45721.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................45821.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................45821.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................45921.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................46021.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................46121.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................46221.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................46221.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................46321.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)(DMA_TCDn_CITER_ELINKYES)...........................................................................................................46321.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)(DMA_TCDn_CITER_ELINKNO)............................................................................................................46421.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........46521.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................46621.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)(DMA_TCDn_BITER_ELINKYES)...........................................................................................................468K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 17