NXP Semiconductors freescale K51 Series Reference Manual

SDHC Data bufferSystem IP Bus or System AHB Bus7-031-24 23-16 15-8 7-015-8 23-16 31-24Figure 49-28. Data swap between system bus and SDHC data buffer in byte little endianmodeSDHC Data bufferSystem IP Bus or System AHB Bus7-015-8 7-0 31-24 23-1615-8 23-16 31-24Figure 49-29. Data swap between system bus and SDHC data buffer in half word bigendian mode49.5.1.1 Write operation sequenceThere are three ways to write data into the buffer when the user transfers data to the card:1. By using external DMA through the SDHC DMA request signal.2. By processor core polling through the IRQSTAT[BWR] bit (interrupt or polling).3. By using the internal DMA.When the internal DMA is not used, (i.e. the XFERTYP[DMAEN] bit is not set when thecommand is sent), the SDHC asserts a DMA request when the amount of buffer spaceexceeds the value set in the WML register, and is ready for receiving new data. At thesame time, the SDHC would set the IRQSTAT[BWR] bit. The buffer write readyinterrupt will be generated if it is enabled by software.When internal DMA is used, the SDHC will not inform the system before all the requirednumber of bytes are transferred (if no error was encountered). When an error occursduring the data transfer, the SDHC will abort the data transfer and abandon the currentblock. The host driver should read the contents of the DSADDR to get the startingaddress of the abandoned data block. If the current data transfer is in multi block mode,the SDHC will not automatically send CMD12, even though the XFERTYP[AC12EN]bit is set. The host driver shall send CMD12 in this scenario and re-start the writeoperation from that address. It is recommended that a software reset for data be appliedbefore the transfer is re-started after error recovery.Functional descriptionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111358 Freescale Semiconductor, Inc.