NXP Semiconductors freescale K51 Series Reference Manual

25.8.2.3 High-Frequency, High-Gain ModeIn high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier.The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low passfrequency filtering as well as hysteresis for voltage filtering and converts the output tologic levels. In this mode, the internal capacitors could be used.25.8.2.4 High-Frequency, Low-Power ModeIn high-frequency, low-power mode, the oscillator uses a gain control loop to minimizepower consumption. As the oscillation amplitude increases, the amplifier current isreduced. This continues until a desired amplitude is achieved at steady-state. In thismode, the internal capacitors could be used, the internal feedback resistor is connected,and no external resistor should be used.The oscillator input buffer in this mode is differential. It provides low pass frequencyfiltering as well as hysteresis for voltage filtering and converts the output to logic levels.25.8.3 CounterThe oscillator output clock (OSC_CLK_OUT) is gated off until the counter has detected4096 cycles of its input clock (XTL_CLK). After 4096 cycles are completed, the counterpasses XTL_CLK onto OSC_CLK_OUT. This counting time-out is used to guaranteeoutput clock stability.25.8.4 Reference Clock Pin RequirementsThe OSC module requires use of both the EXTAL and XTAL pins to generate an outputclock in Oscillator mode, but requires only the EXTAL pin in External clock mode. TheEXTAL and XTAL pins are available for I/O. For the implementation of these pins onthis device, refer to the Signal Multiplexing chapter.25.9 ResetThere is no reset state associated with the OSC module. The counter logic is reset whenthe OSC is not configured to generate clocks.There are no sources of reset requests for the OSC module.ResetK51 Sub-Family Reference Manual, Rev. 6, Nov 2011570 Freescale Semiconductor, Inc.