NXP Semiconductors freescale K51 Series Reference Manual

MC_SRSL field descriptions (continued)Field Description0 Reset not caused by POR1 Reset caused by POR6PINExternal reset pinIndicates reset was caused by an active-low level on the external RESETpin.0 Reset not caused by external reset pin1 Reset caused by external reset pin5COPComputer Operating Properly (COP) WatchdogReset was caused by the COP watchdog timer timing out. This reset source can be blocked by disablingthe watchdog. For more information, see the watchdog chapter.0 Reset not caused by COP timeout1 Reset caused by COP timeout4–3ReservedThis read-only field is reserved and always has the value zero.2LOCLoss-of-clock resetIndicates reset was caused by a loss of external clock. The MCG clock monitor must be enabled for a lossof clock to be detected. See the MCG chapter for information on enabling the clock monitor.0 Reset not caused by a loss of external clock.1 Reset caused by a loss of external clock.1LVDLow-voltage detect resetIf the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit isalso set by POR.0 Reset not caused by LVD trip or POR1 Reset caused by LVD trip or POR0WAKEUPLow-leakage wakeup resetReset was caused by an enabled LLWU module wakeup source while the device was in LLS or VLLSmodes. Wakeup sources in LLS is limited to the RESET pin. In VLLS, any enabled wakeup source causesa reset. This bit is cleared by any reset except WAKEUP.0 Reset not caused by LLWU module wakeup source1 Reset caused by LLWU module wakeup source13.2.3 Power Mode Protection Register (MC_PMPROT)This write-once register allows low power or low leakage modes to be entered. Theactual enabling of the low power or low leakage modes is done by configuring the powermode control register (PMCTRL).Mode Control Memory Map/Register DefinitionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011308 Freescale Semiconductor, Inc.