NXP Semiconductors freescale K51 Series Reference Manual

27.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)This register has a format similar to that for PFB0CR, except it controls the operation offlash bank 1, and the "global" cache control fields are empty.Address: FMC_PFB1CR is 4001_F000h base + 8h offset = 4001_F008hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R B1RWSC[3:0] 0 B1MW[1:0] 0WReset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 0B1DCEB1ICEB1DPEB1IPEB1SEBEWReset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1FMC_PFB1CR field descriptionsField Description31–28B1RWSC[3:0]Bank 1 Read Wait State ControlThis read-only field defines the number of wait states required to access the bank 1 flash memory.The relationship between the read access time of the flash array (expressed in system clock cycles) andRWSC is defined as:Access time of flash array [system clocks] = RWSC + 1The FMC automatically calculates this value based on the ratio of the system clock speed to the flashclock speed. For example, when this ratio is 4:1, the field's value is 3h.27–19ReservedThis read-only field is reserved and always has the value zero.18–17B1MW[1:0]Bank 1 Memory WidthThis read-only field defines the width of the bank 1 memory.00 32 bits01 64 bits10 Reserved11 Reserved16ReservedThis read-only field is reserved and always has the value zero.15–8ReservedThis read-only field is reserved and always has the value zero.7–5ReservedThis read-only field is reserved and always has the value zero.Table continues on the next page...Chapter 27 Flash Memory Controller (FMC)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 591