NXP Semiconductors freescale K51 Series Reference Manual

40.4.3.4 Glitch filter bypassedIn pulse counter mode when the glitch filter is bypassed, the selected input sourceincrements the LPTMR counter register every time it asserts. Before the LPTMR is firstenabled, the selected input source is forced to asserted. This is to prevent the LPTMRcounter register from incrementing if the selected input source is already asserted whenthe LPTMR is first enabled.40.4.4 LPTMR compareWhen the LPTMR counter register equals the value of the LPTMR compare register andincrements, the following events occur:• Timer compare flag is set• LPTMR interrupt is generated if Timer Interrupt Enable is also set• LPTMR hardware trigger is generated• LPTMR counter register is reset if the free running counter bit is clearWhen the LPTMR is enabled, the LPTMR compare register can only be altered when thetimer compare flag is set. When updating the LPTMR compare register, the LPTMRcompare register must be written and the timer compare flag must be cleared before theLPTMR counter has incremented past the new LPTMR compare value.40.4.5 LPTMR counterThe LPTMR counter register increments by one on every:• prescaler clock (time counter mode with prescaler bypassed)• prescaler output (time counter mode with prescaler enabled)• input source assertion (pulse counter mode with glitch filter bypassed)• glitch filter output (pulse counter mode with glitch filter enabled).The LPTMR counter register is reset when the LPTMR is disabled or if the counterregister overflows. If the CSR[TFC] control bit is set then the LPTMR counter register isalso reset whenever the CSR[TCF] status flag is set.The LPTMR counter register continues incrementing when the core is halted in debugmode.Functional descriptionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111006 Freescale Semiconductor, Inc.