NXP Semiconductors freescale K51 Series Reference Manual

SIM_SCGC3 field descriptions (continued)Field Description23–18ReservedThis read-only field is reserved and always has the value zero.17SDHCSDHC Clock Gate ControlThis bit controls the clock gate to the SDHC module.0 Clock disabled1 Clock enabled16–13ReservedThis read-only field is reserved and always has the value zero.12SPI2SPI2 Clock Gate ControlThis bit controls the clock gate to the SPI2 module.0 Clock disabled1 Clock enabled11–5ReservedThis read-only field is reserved and always has the value zero.4ReservedThis read-only field is reserved and always has the value zero.3–1ReservedThis read-only field is reserved and always has the value zero.0ReservedThis read-only field is reserved and always has the value zero.12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)Address: SIM_SCGC4 is 4004_7000h base + 1034h offset = 4004_8034hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0 1LLWU 0VREFCMPUSBOTG 0WReset 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0UART3UART2UART1UART0 0I2C1I2C0 1 0CMTEWM 0WReset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0Chapter 12 System integration module (SIM)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 273