NXP Semiconductors freescale K51 Series Reference Manual

24.3.1 MCG Control 1 Register (MCG_C1)Address: MCG_C1 is 4006_4000h base + 0h offset = 4006_4000hBit 7 6 5 4 3 2 1 0Read CLKS FRDIV IREFS IRCLKEN IREFSTENWriteReset 0 0 0 0 0 1 0 0MCG_C1 field descriptionsField Description7–6CLKSClock Source SelectSelects the clock source for MCGOUTCLK .00 Encoding 0 — Output of FLL or PLL is selected (depends on PLLS control bit).01 Encoding 1 — Internal reference clock is selected.10 Encoding 2 — External reference clock is selected.11 Encoding 3 — Reserved, defaults to 00.5–3FRDIVFLL External Reference DividerSelects the amount to divide down the external reference clock for the FLL. The resulting frequency mustbe in the range 31.25 kHz to 39.0625 kHz (This is required when FLL/DCO is the clock source forMCGOUTCLK . In FBE mode, it is not required to meet this range, but it is recommended in the caseswhen trying to enter a FLL mode from FBE).000 If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.001 If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.010 If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.011 If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.100 If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.101 If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.110 If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is Reserved .111 If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is Reserved .2IREFSInternal Reference SelectSelects the reference clock source for the FLL.0 External reference clock is selected.1 The slow internal reference clock is selected.1IRCLKENInternal Reference Clock EnableEnables the internal reference clock for use as MCGIRCLK.0 MCGIRCLK inactive.1 MCGIRCLK active.0IREFSTENInternal Reference Stop EnableControls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.Table continues on the next page...Memory Map/Register DefinitionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011530 Freescale Semiconductor, Inc.