DMA memory map (continued)Absoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4000_801E Clear Error Register (DMA_CERR) 8W(alwaysreadszero)00h 21.3.11/4484000_801F Clear Interrupt Request Register (DMA_CINT) 8W(alwaysreadszero)00h 21.3.12/4494000_8024 Interrupt Request Register (DMA_INT) 32 R/W 0000_0000h 21.3.13/4494000_802C Error Register (DMA_ERR) 32 R/W 0000_0000h 21.3.14/4524000_8034 Hardware Request Status Register (DMA_HRS) 32 R/W 0000_0000h 21.3.15/4544000_8100 Channel n Priority Register (DMA_DCHPRI3) 8 R/W Undefined 21.3.16/4564000_8101 Channel n Priority Register (DMA_DCHPRI2) 8 R/W Undefined 21.3.16/4564000_8102 Channel n Priority Register (DMA_DCHPRI1) 8 R/W Undefined 21.3.16/4564000_8103 Channel n Priority Register (DMA_DCHPRI0) 8 R/W Undefined 21.3.16/4564000_8104 Channel n Priority Register (DMA_DCHPRI7) 8 R/W Undefined 21.3.16/4564000_8105 Channel n Priority Register (DMA_DCHPRI6) 8 R/W Undefined 21.3.16/4564000_8106 Channel n Priority Register (DMA_DCHPRI5) 8 R/W Undefined 21.3.16/4564000_8107 Channel n Priority Register (DMA_DCHPRI4) 8 R/W Undefined 21.3.16/4564000_8108 Channel n Priority Register (DMA_DCHPRI11) 8 R/W Undefined 21.3.16/4564000_8109 Channel n Priority Register (DMA_DCHPRI10) 8 R/W Undefined 21.3.16/4564000_810A Channel n Priority Register (DMA_DCHPRI9) 8 R/W Undefined 21.3.16/4564000_810B Channel n Priority Register (DMA_DCHPRI8) 8 R/W Undefined 21.3.16/4564000_810C Channel n Priority Register (DMA_DCHPRI15) 8 R/W Undefined 21.3.16/4564000_810D Channel n Priority Register (DMA_DCHPRI14) 8 R/W Undefined 21.3.16/456Table continues on the next page...Chapter 21 Direct Memory Access Controller (eDMA)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 421