NXP Semiconductors freescale K51 Series Reference Manual

38.4.7 Center-Aligned PWM (CPWM) ModeThe center-aligned mode is selected when (QUADEN = 0), (DECAPEN = 0),(COMBINE = 0), and (CPWMS = 1).The CPWM pulse width (duty cycle) is determined by 2 × (CnV − CNTIN) and theperiod is determined by 2 × (MOD − CNTIN)(see the following figure). MOD must bekept in the range of 0x0001 to 0x7FFF because values outside this range can produceambiguous results.In the CPWM mode, the FTM counter counts up until it reaches MOD and then countsdown until it reaches CNTIN.The CHnF bit is set and channel (n) interrupt is generated (if CHnIE = 1) at the channel(n) match (FTM counter = CnV) when the FTM counting is down (at the begin of thepulse width) and when the FTM counting is up (at the end of the pulse width).This type of PWM signal is called center-aligned because the pulse width centers for allchannels are aligned with the value of CNTIN.The other channel modes are not compatible with the up-down counter (CPWMS = 1).Therefore, all FTM channels must be used in CPWM mode when (CPWMS = 1).pulse widthcounter overflowFTM counter =MODperiod2 x (CnV - CNTIN)2 x (MOD - CNTINCNTIN)FTM counter = CNTINchannel (n) match(FTM countingis down)channel (n) match(FTM countingis up)counter overflowFTM counter =MODchannel (n) outputFigure 38-184. CPWM Period and Pulse Width with ELSnB:ELSnA = 1:0If (ELSnB:ELSnA = 0:0) when the FTM counter reaches the value in the CnV register,the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however thechannel (n) output is not controlled by FTM.If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n)match (FTM counter = CnV) when counting down, and it is forced low at the channel (n)match when counting up (see the following figure).Chapter 38 FlexTimer (FTM)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 921