NXP Semiconductors freescale K51 Series Reference Manual

I2Sx_ISR field descriptions (continued)Field DescriptionThis flag bit is set when RX1 or Rx FIFO 1 is loaded with a new value and two-channel mode is selected.RDR1 is cleared when the core reads the RX1 register. If Rx FIFO 1 is enabled, RDR1 is cleared whenthe FIFO is empty. If IER[RIE] and IER[RDR1EN] are set, a receive data 1 interrupt request is issued onsetting of RDR1 bit in case Rx FIFO1 is disabled, if the FIFO is enabled, the interrupt is issued on RFF1assertion. The RDR1 bit is cleared by POR and I2S reset.0 No new data for core to read.1 New data for core to read.14RDR0Receive Data Ready 0.This flag bit is set when RX0 or Rx FIFO 0 is loaded with a new value. RDR0 is cleared when the corereads the RX0 register. If Rx FIFO 0 is enabled, RDR0 is cleared when the FIFO is empty. If IER[RIE] andIER[RDR0EN] are set, a receive data 0 interrupt request is issued on setting of RDR0 bit in case RxFIFO0 is disabled, if the FIFO is enabled, the interrupt is issued on RFF0 assertion. The RDR0 bit iscleared by POR and I2S reset.0 No new data for core to read.1 New data for core to read.13TDE1Transmit Data Register Empty 1.This flag is set whenever data is transferred to TXSR from TX1 register and two-channel mode isselected. If Tx FIFO1 is enabled, this occurs when there is at least one empty slot in TX1 or Tx FIFO1. IfTx FIFO1 is not enabled, this occurs when the contents of TX1 are transferred to TXSR.The TDE1 bit is cleared when the core writes to TX1. If IER[TIE] and IER[TDE1EN] are set, an I2Stransmit data 1 interrupt request is issued on setting of TDE1 bit. The TDE1 bit is cleared by POR and I2Sreset.0 Data available for transmission.1 Data needs to be written by the core for transmission.12TDE0Transmit Data Register Empty 0.This flag is set whenever data is transferred to TXSR from TX0 register. If Tx FIFO 0 is enabled, thisoccurs when there is at least one empty slot in TX0 or Tx FIFO 0. If Tx FIFO 0 is not enabled, this occurswhen the contents of TX0 are transferred to TXSR. The TDE0 bit is cleared when the core writes to TX0.If IER[TIE] and TIE[TDE0EN] are set, an I2S transmit data 0 interrupt request is issued on setting of TDE0bit. The TDE0 bit is cleared by POR and I2S reset.0 Data available for transmission.1 Data needs to be written by the core for transmission.11ROE1Receiver Overrun Error 1.This flag is set when the RXSR is filled and ready to transfer to RX1 register or to Rx FIFO 1 (whenenabled) and these are already full and Two-Channel mode is selected. If Rx FIFO 1 is enabled, this isindicated by RFF1 flag, else this is indicated by the RDR1 flag. The RXSR is not transferred in this case.The ROE1 flag causes an interrupt if IER[RIE] and IER[ROE1EN] are set.The ROE1 bit is cleared by POR and I2S reset. It is also cleared by writing `1' to this bit. Clearing theCR[RE] bit does not affect the ROE1 bit.0 No overrun detected1 Receiver overrun error occurred10ROE0Receiver Overrun Error 0.Table continues on the next page...Memory map/register definitionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111428 Freescale Semiconductor, Inc.