NXP Semiconductors freescale K51 Series Reference Manual

38.3.24 Synchronization Configuration (FTMx_SYNCONF)This register selects the PWM synchronization configuration, SWOCTRL, INVCTRLand CNTIN registers synchronization, if FTM clears the TRIGj bit (where j = 0, 1, 2)when the hardware trigger j is detected.Addresses: FTM0_SYNCONF is 4003_8000h base + 8Ch offset = 4003_808ChFTM1_SYNCONF is 4003_9000h base + 8Ch offset = 4003_908ChFTM2_SYNCONF is 400B_8000h base + 8Ch offset = 400B_808ChBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0HWSOCHWINVCHWOMHWWRBUFHWRSTCNTWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0SWSOCSWINVCSWOMSWWRBUFSWRSTCNTSYNCMODE 0SWOCINVC 0CNTINC 0HWTRIGMODEWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FTMx_SYNCONF field descriptionsField Description31–21ReservedThis read-only field is reserved and always has the value zero.20HWSOCSoftware output control synchronization is activated by a hardware trigger.0 A hardware trigger does not activate the SWOCTRL register synchronization.1 A hardware trigger activates the SWOCTRL register synchronization.19HWINVCInverting control synchronization is activated by a hardware trigger.0 A hardware trigger does not activate the INVCTRL register synchronization.1 A hardware trigger activates the INVCTRL register synchronization.18HWOMOutput mask synchronization is activated by a hardware trigger.0 A hardware trigger does not activate the OUTMASK register synchronization.1 A hardware trigger activates the OUTMASK register synchronization.17HWWRBUFMOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization.Table continues on the next page...Memory Map and Register DefinitionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011902 Freescale Semiconductor, Inc.