NXP Semiconductors freescale K51 Series Reference Manual

Table 10-1. Reference links to related information (continued)Topic Related module ReferenceClocking Clock DistributionRegister access Peripheral buscontrollerPeripheral bridge10.2.1 Port control and interrupt module features• Five 32-pin portsNOTENot all pins are available on the device. See the followingsection for details.• Each 32-pin port is assigned one interrupt.• The digital filter option has two clock source options: bus clock and 1-kHz LPO. The1-kHz LPO option gives users this feature in low power modes.• The digital filter is configurable from 1 to 32 clock cycles when enabled.10.2.2 Clock gatingThe clock to the port control module can be gated on and off using the SCGC5[PORTx]bits in the SIM module. These bits are cleared after any reset, which disables the clock tothe corresponding module to conserve power. Prior to initializing the correspondingmodule, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning offthe clock, make sure to disable the module. For more details, refer to the clockdistribution chapter.10.2.3 Signal multiplexing constraints1. A given peripheral function must be assigned to a maximum of one package pin. Donot program the same function to more than one pin.2. To ensure the best signal timing for a given peripheral's interface, choose the pins inclosest proximity to each other.3. For normal operation of the LCD, use ALT0 LCD functions. The ALT7 LCDfunctions are only available for LCD fault detection.Signal Multiplexing IntegrationK51 Sub-Family Reference Manual, Rev. 6, Nov 2011220 Freescale Semiconductor, Inc.