NXP Semiconductors freescale K51 Series Reference Manual

Table 50-54. I2S receive data interruptsInterrupt RIE ROEn RFFn/RDRnReceive data 0 interrupts (n = 0)Receive data 0 (with exception status) 1 1 1Receive data 0 (without exception) 1 0 1Receive data 1 interrupts (n = 1)Receive data 1 (with exception status) 1 1 1Receive data 1 (without exception) 1 0 150.4.5 Transmit interrupt enable bit descriptionIf the transmit FIFO is not enabled and the IER[TIE] and CR[TE] bits are set:• an interrupt occurs when the corresponding I2S transmit data register empty(ISR[TDE0/1]) flag is set• one value can be written to the I2S_TX0 register (one per channel, in two-channelmode using I2S_TX1)If the transmit FIFO is enabled and the IER[TIE] and CR[TE] bits are set:• an interrupt occurs when either of the I2S transmit FIFO empty (ISR[TFE0/1]) flagsis set• a maximum of 15 values can be written to the I2S ( 15 per channel in two-channelmode, using Tx FIFO 1)When the IER[TIE] bit is cleared, all transmit interrupts are disabled. However, theISR[TDE0/1] bits always indicate the corresponding TX register empty condition, evenwhen the transmitter is disabled by the transmit enable (CR[TE]) bit. Writing data to theTX clears the corresponding ISR[TDE] bit, thus clearing the interrupt.Two transmit data interrupts are available (four in two-channel mode, two per channel):transmit data with exception status and transmit data without exceptions. The followingtable shows the conditions under which these interrupts are generated.Table 50-55. I2S transmit data interruptsInterrupt TIE TUEn TFEn/TDEnTransmit data 0 interrupts (n = 0)Transmit data 1 (with exception status) 1 1 1Table continues on the next page...Chapter 50 Integrated interchip sound (I2S)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1477