NXP Semiconductors freescale K51 Series Reference Manual

SDHC_CMDARG field descriptionsField Description31–0CMDARGCommand ArgumentThe SD/MMC command argument is specified as bits 39-8 of the command format in the SD or MMCspecification.This register is write protected when the PRSSTAT[CDIHB0] bit is set.49.4.4 Transfer Type Register (SDHC_XFERTYP)This register is used to control the operation of data transfers. The host driver shall setthis register before issuing a command followed by a data transfer, or before issuing aresume command. To prevent data loss, the SDHC prevents writing to the bits, that areinvolved in the data transfer of this register, when data transfer is active. These bits areDPSEL, MBSEL, DTDSEL, AC12EN, BCEN and DMAEN.The host driver shall check the PRSSTAT[CDIHB] and the PRSSTAT[CIHB] beforewriting to this register. When the PRSSTAT[CDIHB] is set, any attempt to send acommand with data by writing to this register is ignored; when the PRSSTAT[CIHB] bitis set, any write to this register is ignored.On sending commands with data transfer invovled, it is mandatory that the block size isnon-zero. Besides, block count must also be non-zero, or indicated as single blocktransfer (bit 5 of this register is ‘0’ when written), or block count is disabled (bit 1 of thisregister is ‘0’ when written), otherwise SDHC will ignore the sending of this commandand do nothing. For write command, with all above restrictions, it is also mandatory thatthe write protect switch is not active (WPSPL bit of Present State Register is ‘1),otherwise SDHC will also ignore the command.If the commands with data transfer does not receive the response in 64 clock cycles, i.e.,response time-out, SDHC will regard the external device does not accept the commandand abort the data transfer. In this scenario, the driver should issue the command again tore-try the transfer. It is also possible that for some reason the card responds the commandbut SDHC does not receive the response, and if it is internal DMA (either simple DMAor ADMA) read operation, the external system memory is over-written by the internalDMA with data sent back from the card.The following table shows the summary of how register settings determine the type ofdata transfer.Table 49-7. Transfer Type Register Setting for Various Transfer TypesMulti/Single block select Block count enable Block count Function0 Don't care Don't care Single transferTable continues on the next page...Memory map and register definitionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111312 Freescale Semiconductor, Inc.